PIC18F6680-E/PT Microchip Technology, PIC18F6680-E/PT Datasheet - Page 199
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6680-E/PT
Manufacturer Part Number
PIC18F6680-E/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18F6680-E/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
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Quantity:
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Part Number:
PIC18F6680-E/PT
Manufacturer:
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- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 199 of 496
- Download datasheet (9Mb)
17.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal
transmit/receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
SSPSTAT
Legend:
Name
mode,
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISF7
PSPIE
PSPIP
WCOL
PSPIF
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
the
module
TRISF6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
will
TRISF5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
continue
PIC18F6585/8585/6680/8680
TRISF4
INT0IE
Bit 4
TXIF
TXIE
TXIP
CKP
P
to
TRISF3
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also a SMP bit which controls when the data is
sampled.
Standard SPI Mode
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISF2
SSPM2
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
TMR2IE
TMR2IP
TMR2IF
TRISF1
SSPM1
INT0IF
Bit 1
UA
SPI BUS MODES
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
TMR1IF 0000 0000 0000 0000
TRISF0 1111 1111 uuuu uuuu
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
BF
CKP
Control Bits State
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0
0
1
1
POR, BOR
Value on
DS30491C-page 197
CKE
Value on
all other
Resets
1
0
1
0
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