APDS-9801 Avago Technologies US Inc., APDS-9801 Datasheet - Page 11

INTEGRATED DIGITAL PS AND ALS

APDS-9801

Manufacturer Part Number
APDS-9801
Description
INTEGRATED DIGITAL PS AND ALS
Manufacturer
Avago Technologies US Inc.
Type
Analog Ambient Light Sensor and Digital Proximity Sensorr
Datasheet

Specifications of APDS-9801

Peak Wavelength
940 nm
Maximum Light Current
83 uA
Maximum Dark Current
300 nA
Maximum Rise Time
1000 ns
Maximum Fall Time
300 ns
Mounting Style
SMD/SMT
Product
Integrated Ambient Light and Proximity Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
APDS-9801
Manufacturer:
LEGERITY
Quantity:
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Part Number:
APDS-9801
Manufacturer:
Avago Technologies
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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Note 1: Figure 3 Definition of transmit burst pulses
Duty cycle = t/Pclk
Delay
Note 2: Interrupt Status Implementation
The following diagram explained how the positive threshold interrupt status and negative threshold interrupt status is
implemented. ADC Data and Interrupt threshold is compared. The output is high or low depends on the comparison
result. The detection of rising edge of the comparator set the positive threshold interrupt status bit to ‘1’ . The detection
of falling edge of the comparator set the negative threshold interrupt status bit to ‘1’ .
Comparator output waveform:
11
Interrupt Threshold
If rising edge is detected, Positive
Threshold interrupt status bit is set to ‘1’.
After reading the status bit, write ‘1’
to bit 6 of the command register to
clear the status. Wait for another
interrupt status assert.
‘1’ if ADC Data > Interrupt Threshold
Pclk
ADC Data
= the time between the last burst pulse to the first burst pulse of the next burst
t
N x pulses
+
1
st
burst
Comparator Output
‘0’ if ADC Data < Interrupt Threshold
If falling edge is detected, Negative
Threshold interrupt status bit is set to ‘1’.
After reading the status bit, write ‘1’
to bit 6 of the command register to
clear the status. Wait for another
interrupt status assert.
Delay
2
nd
burst

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