ADNS-3060 Avago Technologies US Inc., ADNS-3060 Datasheet - Page 19

• Manufacturer Part Number: ADNS-3060
• Description: Optical Mouse Sensor,DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-3060

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q2073278B

Frame Capture
This is a fast way to download a full array of pixel values
from a single frame. This mode disables navigation and
overwrites any downloaded firmware. A hardware reset
is required to restore navigation, and the firmware must
be reloaded afterwards if required.
To trigger the capture, write to the Frame_Capture reg-
ister. The next available complete 1 2/3 frames (1536
values) will be stored to memory. The data are is retrieved
by reading the Pixel_Burst register once using the nor-
mal read method, after which the remaining bytes are
clocked out by driving SCLK at the normal rate. The byte
time must be at least t
read before the data is ready, it will return all zeros.
To read a single frame, read a total of 900 bytes. The next
636 bytes will be approximately 2/3 of the next frame.
The first pixel of the first frame (1st read) has bit 6 set to
Figure 24. Frame capture burst mode timing
19
SCLK
MOSI
MISO
NCS
Notes:
1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. t
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.
CAPTURE
t
>120ns
NCS-SCLK
= 10μs + 3 frame periods.
frame capture reg write
LOAD
address
. If the Pixel_ Burst register is
data
t
CAPTURE
P0 bit 6 set to 1
t
SRAD
pixel dump reg read
≥
address
50μs
1 as a start-of-frame marker. The first pixel of the second
partial frame (901st read) will also have bit 6 set to 1. All
other bytes have bit 6 set to zero. The MSB of all bytes is
set to 1. If the Pixel_Burst register is read past the end
of the data (1537 reads and on) , the data returned will
be zeros.
After the download is complete, the micro-controller
must raise the NCS line for at least t
burst mode. The read may be aborted at any time by
raising NCS.
Alternatively, the frame data can also be read one byte at
a time from the Frame_Capture register. See the register
description for more information.
enter burst
mode
≥
P0
t
10μs
LOAD
≥
all MSB = 1
t
P1
LOAD
10μs
soonest to begin again
P899
exit burst mode
BEXIT
t
BEXIT
see note 2
to terminate
≥
frame capture reg
4μs
address
≥
10μs