AD9552/PCBZ Analog Devices Inc, AD9552/PCBZ Datasheet - Page 13

• Manufacturer Part Number: AD9552/PCBZ
• Description: Oscillator Frequency Upconverter Eval Board
• Manufacturer: Analog Devices Inc

Specifications of AD9552/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Generator
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9552
• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9552
• Primary Attributes: 6.6 MHz ~ 112.5 MHz Input
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
PRESET FREQUENCY RATIOS
The frequency selection pins (A[2:0] and Y[5:0]) allow the user
to hardwire the device for preset input and output divider values
based on the pin logic states (see Figure 19). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
Use the serial I/O port to change the divider values from the
preset values provided by the A[2:0] and Y[5:0] pins.
The A[2:0] pins select one of eight input reference frequencies
(see Table 9). The user supplies the input reference frequency by
connecting a single-ended clock signal to the REF pin or a crystal
resonator across the XTAL pins. If the A[2:0] pins select 10 MHz,
12 MHz, 12.8 MHz, or 16 MHz, the input frequency to the AD9552
doubles internally. Alternatively, if Register 0x1D[2] is set to 1,
the input frequency doubles.
Table 9. Input Reference Frequency Selection Pins
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
SERIAL
REFA
XTAL
XTAL
PORT
A2:0
Y5:0
A0
0
1
0
1
0
1
0
1
3
3
6
CONTROL
TUNING
PRECONFIGURED
DIVIDER VALUES
REGISTER BANK
Reference Frequency (MHz)
10.00
12.00
12.80
16.00
19.20
19.44
20.00
26.00
DETECTOR
2×
Figure 19. Detailed Block Diagram
N, MOD, FRAC, P
DETECT
Rev. C | Page 13 of 32
LOCKED
LOCK
PFD
0
, P
CHARGE
PUMP
1
FRAC
MOD,
MODULATOR
N
The Y[5:0] pins select the appropriate feedback and output dividers
to synthesize the output frequencies (see Table 10). The output
frequencies provided in Table 10 are exact; that is, the number of
decimal places displayed is sufficient to maintain full precision.
Where a decimal representation is not practical, a fractional
multiplier is used.
The VCO and output frequency shift in frequency by a ratio of the
reference frequency used vs. the frequency specified in Table 9.
Note that the VCO frequency must stay within the minimum and
maximum range specified in Table 1. Typically, the selection of
the VCO frequency band, as well as the gain adjustment, by the
external pin strap occurs as part of the device’s automatic VCO
calibration process, which initiates at power up (or reset). If the
user changes the VCO frequency band via the SPI interface,
however, a forced VCO calibration should be initiated by first
enabling SPI control of the VCO calibration (Register 0x0E[2] = 1)
and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).
1
N = 4N
FILTER
Σ-Δ
3350MHz TO
1
4 OR 5
4050MHz
+ N
VCO
0
N
4 TO 11
P
0
P
0
AD9552
, P
1 TO 63
P
1
1
2
2
OUT2
OUT1
AD9552