AD9552/PCBZ Analog Devices Inc, AD9552/PCBZ Datasheet - Page 18

• Manufacturer Part Number: AD9552/PCBZ
• Description: Oscillator Frequency Upconverter Eval Board
• Manufacturer: Analog Devices Inc

Specifications of AD9552/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Generator
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9552
• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9552
• Primary Attributes: 6.6 MHz ~ 112.5 MHz Input
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9552
3.
It is imperative that long division be used to obtain the correct
results. Avoid the use of a calculator or math program, because
these do not always yield correct results due to internal rounding
and/or truncation. Some calculators or math programs may be up
to the task if they can handle very large integer operations, but such
are not common.
The P
valid. However, note that they yield only three valid ODF
values (35, 36, and 40) from the original range of 34 to 40.
Determine the feedback divider values for the PLL.
Repeat this step for each ODF when multiple ODFs exist
(for example, 35, 36, and 40 in the case of Table 12).
To calculate the feedback divider values for a given ODF,
use the following equation:
Note that the left side of the equation contains variables with
known quantities. Furthermore, the values are necessarily
rational, so the left side is expressible as a ratio of two inte-
gers, X and Y. Following is an example equation.
In the context of the AD9552, X/Y is always an improper
fraction. Therefore, it is expressible as the sum of an integer,
N, and the proper fraction, R/Y (R and Y are integers).
This particular example yields N = 148, Y = 1664, and
R = 1228. To arrive at this result, use long division to convert
the improper fraction, X/Y, to an integer (N) and a proper
fraction (R/Y). Note that dividing Y into X by means of
long division yields an integer, N, and a remainder, R. The
proper fraction has a numerator (R, the remainder) and a
denominator (Y, the divisor), as shown in Figure 21.
⎛
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎜
⎝
247
Y
X
625
1664
f
f
OUT
=
REF
,
500
26
⎡
⎢ ⎣
N
0
1
66
64
and P
+
⎞
⎟
⎟
⎠
=
⎤
⎥ ⎦
Y
R
×
⎞
⎟
⎟
⎟
⎟
⎠
N +
ODF
1
×
Y X
Figure 21. Example Long Division
combinations listed in Table 12 are all equally
–NY
Y
6
R
N
R
=
=
625
Y
X
26
(
66
(
64
)(
Y
X
)
) 6
= N +
=
247
1664
Y
R
,
500
=
Y
X
Rev. C | Page 18 of 32
In the example, N = 148 and R/Y = 1228/1664, which reduces
to R/Y = 307/416. These values of N, R, and Y constitute the
following respective feedback divider values:
N = 148, FRAC = 307, and MOD = 416.
The only caveat is that N and MOD must meet the constraints
given in the Output/Input Frequency Relationship section.
In the example, FRAC is nonzero, so the division value is an
integer plus the fractional component, FRAC/MOD. This
implies that the feedback SDM is necessary as part of the
feedback divider. If FRAC = 0, the feedback division factor
is an integer and the SDM is not required (it can be bypassed).
Although the feedback divider values obtained in this way
provide the proper feedback divide ratio to synthesize the exact
output frequency, they may not yield optimal jitter performance
at the final output. One reason for this is that the value of MOD
defines the period of the SDM, which has a direct impact on the
spurious output of the SDM. Specifically, in the spectral band
from dc to f
MOD. Thus, the spectral separation (Δf) of the spurs associated
with the feedback SDM is
Because the SDM is in the feedback path of the PLL, these spurs
appear in the output signal as spurious components offset by Δf
from f
large spurs with relatively large frequency offsets from f
whereas a large MOD value produces smaller spurs but more
closely spaced to f
impact on the spurious content (that is, jitter) at OUT1.
Generally, the largest possible MOD value yields the smallest spurs.
Thus, it is desirable to scale MOD and FRAC by the integer part
of 2
example, the value of MOD is 416, yield-ing a scale factor of 2520
(the integer part of 220/416). A scale factor of 2520 leads to FRAC
= 307 × 2520 = 773,640 and MOD = 416 × 2520 = 1,048,320.
LOW DROPOUT (LDO) REGULATORS
The AD9552 is powered from a single 3.3 V supply and contains
on-chip LDO regulators for each function to eliminate the need
for external LDOs. To ensure optimal performance, each LDO
output should have a 0.47 μF capacitor connected between its
access pin and ground, and this capacitor should be kept as
close to the device as possible.
20
Δ
divided by the value of MOD obtained previously. In the
OUT1
f
=
. Therefore, a small MOD value pro-duces relatively
MOD
f
PFD
PFD
, the SDM exhibits spurs at intervals of f
OUT1
. Clearly, the value of MOD has a direct
PFD
OUT1
/
,