AD9552/PCBZ Analog Devices Inc, AD9552/PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9552/PCBZ
• Description: Oscillator Frequency Upconverter Eval Board
• Manufacturer: Analog Devices Inc

Specifications of AD9552/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Generator
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9552
• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9552
• Primary Attributes: 6.6 MHz ~ 112.5 MHz Input
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 19.
Address
0x0A
0x0B
0x0C
0x0D
Bit
[7:0]
7
6
[5:4]
3
2
1
0
7
6
[5:4]
3
2:0
[7:6]
[5:1]
0
Bit Name
Charge pump current control
Enable SPI control of charge
pump current
Enable SPI control of
antibacklash period
CP mode
Enable CP mode control
PFD feedback input edge control
PFD reference input edge control
Force VCO to midpoint frequency
Unused
CP offset current polarity
CP offset current
Enable CP offset current control
Reserved
Antibacklash control
Unused
PLL lock detector power-down
Description
These bits set the magnitude of the PLL charge pump current. The granularity is
~3.5 μA with a full-scale magnitude of ~900 μA. Register 0x0A is ineffective unless
Register 0x0B[7] = 1. Default is 0x80, or ~448 μA.
Controls functionality of Register 0x0A.
0 = the device automatically controls the charge pump current (default).
1 = charge pump current defined by Register 0x0A.
Controls functionality of Register 0x0D[7:6].
0 = the device automatically controls the antibacklash period (default).
1 = antibacklash period defined by Register 0x0D[7:6].
Controls the mode of the PLL charge pump.
00 = tristate.
01 = pump up.
10 = pump down.
11 = normal (default).
Controls functionality of Bits[5:4] (CP mode).
0 = the device automatically controls the charge pump mode (default).
1 = charge pump mode is defined by Bits[5:4].
Selects the polarity of the active edge of the PLL’s feedback input.
0 = positive edge (default).
1 = negative edge.
Selects the polarity of the active edge of the PLL’s reference input.
0 = positive edge (default).
1 = negative edge.
Selects VCO control voltage functionality.
0 = normal VCO operation (default).
1 = force VCO control voltage to midscale.
Unused.
Selects the polarity of the charge pump offset current of the PLL. This bit is ineffective
unless Bit 3 = 1.
0 = pump up (default).
1 = pump down.
Controls the magnitude of the charge pump offset current of the PLL as a fraction of
the value in Register 0x0A. This bit is ineffective unless Bit 3 = 1.
00 = 1/2 (default).
01 = 1/4.
10 = 1/8.
11 = 1/16.
Controls functionality of Bits[6:4].
0 = the device automatically controls charge pump offset current (default).
1 = charge pump offset current defined by Bits[6:4].
Controls the PFD antibacklash period of the PLL. These bits are ineffective unless
Register 0x0B[6] = 1.
00 = minimum (default).
01 = low.
10 = high.
11 = maximum.
Unused.
Controls power-down of the PLL lock detector.
0 = lock detector active (default).
1 = lock detector powered down.
Rev. C | Page 25 of 32
AD9552