IPR-FFT Altera, IPR-FFT Datasheet - Page 12

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–8
Table 1–9. Performance with the Burst Data Flow Architecture—Cyclone III Devices (Part 2 of 2)
Stratix III Devices
Table 1–10. Performance with the Streaming Data Flow Engine Architecture—Stratix III Devices
Table 1–11. Performance with the Variable Streaming Data Flow Engine Architecture—Stratix III Devices
FFT MegaCore Function User Guide
Notes to
(1) In the burst I/O data flow architecture, you can specify the number of engines in the FFT MegaWizard interface. You may choose from one to
(2) Transform time is the time frame when the input block is loaded until the first output sample (corresponding to the input block) is output.
(3) Block throughput is defined as the minimum number of cycles between two successive start-of-packet (sink_sop) pulses.
Floating
Note to
(1) EP3SL70F780C2 device.
Point Type
Points
Points
1024
4096
4096
Floating
Floating
256
Fixed
Fixed
Fixed
two single-output engines in parallel, or from one, two, or four quad-output engines in parallel.
Transform time does not include the time to unload the full output data block.
Table
Table
(1)
Single Output
Combinational
Architecture
1–11:
1–9:
Points
1024
4096
1024
4096
1
256
256
Engine
ALUTs
2094
2480
2357
Table 1–10
adders complex multiplier structure, for data and twiddle width 16, for Stratix III
(EP3SE50F780C2) devices.
Table 1–11
and bit-reversed outputs, for width 16 (32 for floating point), for Stratix III
(EP3SE50F780C2) devices.
The variable streaming with fixed-point number representation uses natural word
growth, therefore the multiplier requirement is larger compared with the equivalent
streaming FFT with the same number of points.
If you want to significantly reduce M9K memory utilization, set a lower f
Combinational
14059
18019
22026
ALUTs
2511
3476
4480
Engines
Number of
Registers
2
Logic
3715
4458
4545
shows the variable streaming data flow performance, with in order inputs
shows the streaming data flow performance, using the 4 multipliers /2
(1)
Registers
13424
16560
19717
(MHz)
Logic
fMAX
3927
5244
6628
219
Memory
155904
622848
39168
(Bits)
Calculation Time
Cycles
12329
Memory
170639
140750
568579
10239
42218
34728
(Bits)
Transform
Memory
(M9K)
20
20
76
Time (μs)
56.28
Memory
(M9K)
150
(2)
16
23
42
64
95
18 × 18
Blocks
Data Load & Transform
12
12
12
Cycles
16495
18 × 18
Blocks
Calculation
20
28
36
48
64
80
Chapter 1: About This MegaCore Function
(MHz)
442
413
388
f
Time (μs)
MAX
© December 2010 Altera Corporation
(MHz)
Performance and Resource Utilization
341
323
320
303
286
286
f
75.3
MAX
10024
Count
Clock
Cycle
4096
Clock
Cycle
Count
256
1024
4096
1024
4096
256
256
Cycles
Block Throughput
20605
MAX
Transform
Time (μs)
Transform
(3)
Time (μs)
Time (μs)
target.
10.57
14.33
0.58
2.48
0.75
3.17
12.8
0.84
3.58
94.06