IPR-FFT Altera, IPR-FFT Datasheet - Page 50

• Manufacturer Part Number: IPR-FFT
• Description: IP CORE Renewal Of IP-FFT
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-FFT

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Features: Bit-Accurate MATLAB Models, Radix-4 And Mixed Radix-4/2 Implementations
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Fast Fourier Transform Processor
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–16
Table 3–3. Parameters (Part 3 of 3)
Signals
Table 3–4. Avalon-ST Signals (Part 1 of 2)
FFT MegaCore Function User Guide
Use M-RAM or M144K blocks
Implement appropriate logic
functions in RAM
clk
reset_n
sink_eop
sink_error
sink_imag
sink_ready
Signal Name
Parameter
f
Direction
Input
Input
Input
Input
Input
Output
Table 3–4
For more information about the Avalon-ST interface, refer to the
Interface
clk
reset_n
endofpacket
error
data
ready
Specification.
On or Off
On or Off
Avalon-ST Type
shows the Avalon-ST interface signals.
Value
1
1
1
2
data precision
width
1
Implements suitable data RAM blocks within the FFT MegaCore
function in M-RAM (M144K in Stratix III and Stratix IV devices)
to reduce M4K (M9K) RAM block usage, in device families that
support M-RAM blocks.
Not available for variable streaming achitecture, or in the
Cyclone series of device families, or in Stratix V devices.
Uses embedded RAM blocks to implement internal logic
functions, for example, tapped delay lines in the FFT MegaCore
function. This option reduces the overall logic element count.
Not available for variable streaming architecture.
Size
Clock signal that clocks all internal FFT engine
components.
Active-low asynchronous reset signal.This signal
is detected on the rising edge of clk, and it must
be asserted at least one clk clock cycle.
Therefore, reset_n can be safely deasserted on
or following the clk rising edge that follows the
first clk rising edge after reset_n assertion.
Indicates the end of the incoming FFT frame.
Indicates an error has occurred in an upstream
module, because of an illegal usage of the
Avalon-ST protocol. The following errors are
defined (refer to
■
■
■
■
If this signal is not used in upstream modules, set
to zero.
Imaginary input data, which represents a signed
number of data precision bits.
Asserted by the FFT engine when it can accept
data. It is not mandatory to provide data to the FFT
during ready cycles.
00 = no error
01 = missing start of packet (SOP)
10 = missing end of packet (EOP)
11 = unexpected EOP
Description
Table
© December 2010 Altera Corporation
Description
Chapter 3: Functional Description
3–6):
Avalon Streaming
Signals