IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 18

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Specify Parameters
Complete the Qsys System
f
f
For more information about the Qsys system interconnect, refer to the
Interconnect
Specifications.
For more information about the Qsys tool and the Quartus II software, refer to the
System Design with Qsys
II Help.
To specify parameters for your IP core using the Qsys flow, follow these steps:
1. Create a new Quartus II project using the New Project Wizard available from the
2. On the Tools menu, click Qsys (Beta).
3. On the System Contents tab, double-click the name of your IP core to add it to
4. Specify the required parameters in all tabs in the Qsys tool. For detailed
5. Click Finish to complete the IP core instance and add it to the system.
To complete the Qsys system, follow these steps:
1. Add and parameterize any additional components.
2. Connect the components using the Connection panel on the System Contents tab.
3. In the Export As column, enter the name of any connections that should be a
4. If you intend to simulate your Qsys system, on the Generation tab, turn on one or
5. If your system is not part of a Quartus II project and you want to generate
File menu.
your system. The relevant parameter editor appears.
explanations of these parameters, refer to the “Parameter Settings” chapter in this
document.
1
1
1
top-level Qsys system port. If the Export As column is not present, click the
Project Settings tab and turn off Use SOPC Builder port naming.
more options under Simulation to generate desired simulation files.
synthesis RTL files, turn on Create synthesis RTL files.
If your design includes external memory interface IP cores, you must turn
on Generate power of two bus widths on the PHY Settings tab when
parameterizing those cores.
Some IP cores provide preset parameters for specific applications. If you
wish to use preset parameters, click the arrow to expand the Presets list,
select the desired preset, and then click Apply. To modify preset settings, in
a text editor edit the <installation directory>\ip\altera\uniphy\lib\<IP
core>.qprs file.
The Finish button may be unavailable until all parameterization errors
listed in the messages window are corrected.
chapter in volume 1 of the Quartus II Handbook and to the
section in volume 1 of the Quartus II Handbook and to Quartus
Qsys System Integration Tool Design Flow
December 2010 Altera Corporation
Chapter 2: Getting Started
Avalon Interface
Qsys