IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 65

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Functional Description—Example Top-Level Project
Example Driver
December 2010 Altera Corporation
Address and Burst Length Generation
Example Driver Signals
Block Read and Write Generation
During the block read and write generation state of the driver, the traffic generator
block generates a parameterizable number of write operations followed by the same
number of read operations. The specific addresses generated for the blocks are chosen
by the specific substates. The burst length of each block operation can be
parameterized by a range of acceptable burst lengths.
The traffic generator block can perform sequential or random addressing.
Sequential Addressing
The sequential addressing substate defines a traffic pattern where addresses are
chosen in sequential order starting from a user definable address. The number of
operations in this substate is parameterizable.
Random Addressing
The random addressing substate defines a traffic pattern where addresses are chosen
randomly over a parameterizable range. The number of operations in this substate is
parameterizable.
Sequential and Random Interleaved Addressing
The sequential and random interleaved addressing substate defines a traffic pattern
where addresses are chosen to be either sequential or random based on a
parameterizable ratio. The acceptable address range is parameterizable as is the
number of operations to perform in this substate.
Table 7–1
Table 7–1. Driver Signals (Part 1 of 2)
clk
reset_n
avl_ready
avl_write_req
avl_read_req
avl_addr
avl_size
avl_wdata
avl_rdata
avl_rdata_valid
pnf_per_bit
pnf_per_bit_
persist
Signal
lists the signals used by the example driver.
Width
24
72
72
3
avl_ready
avl_write_req
avl_read_req
avl_addr
avl_size
avl_wdata
avl_rdata
avl_rdata_valid
pnf_per_bit
pnf_per_bit_persist
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Signal Type
External Memory Interface Handbook Volume 3
7–3