IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 69

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Table 8–1. Latency (In Full-Rate Memory Clock Cycles)
Variable Controller Latency
December 2010 Altera Corporation
Notes to
(1) RL = read latency.
(2) Latency is the number of cycles between the first register of the current stage capturing cmd/data, and the first register in the next stage
(3) Latency shown is best case, for maximum performance specifications. Latency may be higher due to protocol requirements; controller latency
capturing cmd/data.
may be lower for slower frequencies.
Rate
Half
Full
Table
8–1:
1
Command
Address and
Controller
Altera defines read and write latencies in terms of memory clock cycles. These
latencies apply to supported device families
types of latencies that exists while designing with memory controllers—read and
write latencies, which have the following definitions:
■
■
For a half-rate controller, the local side frequency is half of the memory interface
frequency. For a full-rate controller, the local side frequency is equal to the memory
interface frequency.
Table 8–1
.
The variable controller latency feature allows you to take advantage of lower latency
for variations designed to run at lower frequency. When deciding whether to vary the
controller latency from the default value of 1, be aware of the following
considerations:
■
■
If you select a latency value that is inappropriate for the target frequency, the system
displays a warning message in the text area at the bottom of the parameter editor.
1
2
Read latency—the amount of time it takes for the read data to appear at the local
interface after initiating the read request.
Write latency—the amount of time it takes for the write data to appear at the
memory interface after initiating the write request.
Reduced latency can help acheive a reduction in resource usage and clock cycles in
the controller, but might result in lower f
Increased latency can help acheive greater f
cycles in the controller and result in increased resource usage.
(3)
shows the latency in full rate memory clock cycles.
and Command
PHY Address
1
2
1.5, 2.0, 2.5
1.5, 2.0, 2.5
Maximum
Memory
(Note 2)
Read
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
RL 2.5: 4.5
RL 2.5: 7.5
RL 1.5: 4.5
RL 2.0: 4.0
RL 1.5: 6.5
RL 2.0: 6.0
PHY Read
Return
MAX
(Table 1–2 on page
MAX
.
(1)
(1)
, but might consume more clock
External Memory Interface Handbook Volume 3
RL 2.5: 14
RL 2.5: 9
Round Trip
RL 1.5: 12
RL 2.0: 12
RL 1.5: 8
RL 2.0: 8
1–2). There are two
(1)
(1)
8. Latency
without Memory
RL 2.5: 11.5
RL 2.5: 6.5
RL 1.5: 10.5
RL 2.0: 10.0
Round Trip
RL 1.5: 6.5
RL 2.0: 6.0
(1)
(1)