IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 6
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IPR-RLDRAMII
Manufacturer Part Number
IPR-RLDRAMII
Description
IP CORE Renewal Of IP-RLDRAMII
Manufacturer
Altera
Series
Memory Controllers - SDRAMr
Type
MegaCorer
Specifications of IPR-RLDRAMII
Software Application
IP CORE, Memory Controllers, SDRAM
Tool Function
Intellectual Property (IP) Core
Supported Devices
HardCopy, Stratix
Function
RLDRAM II Controller
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
RLDRAM II Controller MegaCore Function v7.1 Issues
6
RLDRAM II Controller MegaCore Function v7.1 Errata Sheet
Workaround
For VHDL gate-level simulations, in the simulation/modelsim directory
follow these steps:
1.
2.
For Verilog HDL gate-level simulations, in the simulation/modelsim
directory follow these steps:
1.
2.
3.
initial $sdf_annotate("<project name>_v.sdo");
Solution Status
This issue will be fixed in a future version of the RLDRAM II Controller
MegaCore function.
Unpredictable Results for Gate-Level Simulations (HardCopy II
Devices only)
Gate-level simulations may not work as expected on HardCopy
devices, because HardCopy II timing is preliminary in the Quartus II
software version 5.1.
Affected Configurations
This issue affects all configurations on HardCopy II devices.
Design Impact
There is no design impact.
Workaround
This issue has no workaround.
Rename <filename>.vho file to <project name>.vho.
Rename <filename>.sdo file to <project name>_vhd.sdo.
Rename the <filename>.vo file to <project name>.vo.
Rename the <filename>.sdo file to <project name>_v.sdo.
In the <project name>.vo file change the following line to point to the
<project name>_v.sdo file:
Altera Corporation
®
II