IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet

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... MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com RLDRAM II Controller MegaCore Version: Document Date: 9.1 November 2009 ...

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... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...

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... Chapter 3. Getting Started Design Flow ............................................................................................................................................ 3–1 RLDRAM II Controller Walkthrough ................................................................................................. 3–2 Create a New Quartus II Project .................................................................................................... 3–3 Launch IP Toolbench ....................................................................................................................... 3–4 Step 1: Parameterize ......................................................................................................................... 3–5 Step 2: Constraints ............................................................................................................................ 3–7 Step 3: Set Up Simulation ................................................................................................................ 3–8 Step 4: Generate ................................................................................................................................ 3–8 Simulate the Example Design ............................................................................................................ 3–11 Altera Corporation MegaCore Version 9.1 Contents iii ...

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... Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 3–12 Edit the PLL .......................................................................................................................................... 3–13 Compile the Example Design ............................................................................................................ 3–14 Program a Device ................................................................................................................................ 3–15 Implement Your Design ..................................................................................................................... 3–15 Set Up Licensing .................................................................................................................................. 3–15 Additional Information Revision History ......................................................................................................................................... i How to Contact Altera ............................................................................................................................... i Typographic Conventions ....................................................................................................................... ii iv RLDRAM II Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation ...

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... For more information about this release, refer to the Release Notes and Altera verifies that the current version of the Quartus compiles the previous version of each MegaCore function. The IP Library Release Notes and Errata verification. Altera does not verify compilation with MegaCore function versions older than one release ...

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... RLDRAM II command signals. The RLDRAM II controller is optimized for Altera Stratix II devices and has preliminary support for Stratix II GX and HardCopy II devices. The advanced features available in these devices allow you to interface directly to RLDRAM II devices. Figure 1– ...

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... Clock PLL ( 1 ) Note to Figure 1–1: (1) Non-DQS mode only. IP Toolbench generates the following items: ■ ■ Altera Corporation November 2009 Local Interface Control Logic (Encrypted) Datapath (Clear Text) RLDRAM II Controller A testbench, which instantiates the example design A synthesizable example design which instantiates the following ...

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... Performance and Resource Utilization OpenCore Plus Evaluation With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions: ■ ■ ■ ■ You only need to obtain a license for the megafunction when you are completely satisfied with its functionality and performance, and want to take your design to production ...

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... Table 1–5 (ALUTs) and logic registers for the RLDRAM II controller. Table 1–5. Typical Size Stratix II and Stratix II GX Notes to (1) Altera Corporation November 2009 shows the clock frequency support for Stratix II and Stratix GX Speed Grade –3 –4 –5 shows typical sizes in combinational adaptive look-up tables ...

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... Performance and Resource Utilization 1–6 RLDRAM II Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation November 2009 ...

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... The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and <signal>_1 are present. (3) Non-DQS mode only. (4) DQS mode only. Altera Corporation November 2009 2. Functional Description shows the RLDRAM II Controller MegaCore function block Note (1) , (2) RLDRAM II Controller ...

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... Places write data onto the rldramii_dq[] or rldramii_d[] bus during the correct clock cycles Captures the read data using dedicated data strobe signal (DQS) delay circuitry during DQS mode or an external capture clock in non- DQS mode 2–16. MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Read READ Low Write WRITE Low Auto AREF Low Refresh Datapath Figure 2–2 on page 2–4 Altera Corporation November 2009 shows the RLDRAM II control signals generated by the control rldramii rldramii _we_n_0 _ref_n_0 Don’t care Don’t care Low Low High High ...

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... Captures RLDRAM II read data and data valid (QVLD) signals with: In DQS mode, a delayed rldramii_qk[] generated by the ● dedicated DQS delay circuitry In non-DQS mode, an external capture clock ● MegaCore Version 9.1 rldramii_a_0[] rldramii_ba_0[] rldramii_cs_n_0 rldramii_ref_n_0 rldramii_we_n_0 rldramii_clk[] rldramii_clk_n[] rldramii_dm[] rldramii_dq[] rldramii_d[] rldramii_q[] rldramii_qk[] rldramii_qvld[] Altera Corporation November 2009 ...

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... IP Toolbench generates a clear-text VHDL or Verilog HDL datapath, which matches your custom variation. If you are designing your own controller, Altera recommends that you use this module as your datapath. Figure 2–3 writing to the datapath. ...

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... QVLD group module. The rldramii_qvld[] signal is captured in the same way that the DQS group module captures the read data. In DQS mode, the delayed rldramii_qk[] captures rldramii_qvld[]; in non-DQS mode, the external clock captures rldramii_qvld[]. shows the Stratix II series and HardCopy II MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the DQ pin. This inversion is automatic if you use an altdq megafunction for the DQ pins. Figure 2–5 on page 2–8 devices DQS group block diagram (DQS mode, SIO devices). Altera Corporation November 2009 Note dq_oe ...

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... The example RLDRAM II DQS mode Two 18-bit CIO RLDRAM II devices. Each RLDRAM II device has two rldramii_qk[] data strobes, each associated with 9-bits of data 36-bit RLDRAM II interface, which requires a 72-bit datapath interface MegaCore Version 9.1 Note (1), (2), ( DQS DQS Delay Altera Corporation November 2009 ...

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... Registers Registers capture_clk[1] control_qvld[1] Registers control_rdata[17:0] control_rdata[53:36] Registers Registers capture_clk[0] control_qvld[0] Registers Figure 2–6 interface configurations: ■ Altera Corporation November 2009 Datapath DQS Group 3 Optional Read Pipeline Data Logic DQS Group 2 Optional Read Pipeline Data Logic Optional QVLD Pipeline ...

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... RLDRAM II 1 capture data is associated with ● capture_clk[1], which is the delayed rldramii_qk[2] shows the read data and data strobes at the memory interface Figure MegaCore Version 9.1 2–6. Figure 2–8 shows how the Altera Corporation November 2009 ...

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... Figure 2–8. Datapath Interface Figure 2–8 delayed rldramii_qk[] signal is located in the lower half-bit locations of control_rdata[]. Any read data captured on the falling edge of the delayed rldramii_qk[] signal is located in the upper half-bit locations Altera Corporation November 2009 RLDRAM II Device 1 M rldramii_qk[3] I ...

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... For MegaCore functions, the untethered time out is 1 hour; the tethered time out value is indefinite. Megafunctions. “PLL Configuration” on page 2–12 “Example Design” on page 2–14 “Constraints” on page 2–16 MegaCore Version 9.1 and AN 320: OpenCore Plus Altera Corporation November 2009 ...

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... The recommended configuration for implementing the RLDRAM II controller in Stratix II series and HardCopy II devices is to use a single enhanced PLL to produce all the required clock signals. No external clock buffer is required as the Altera device can generate clock signals for the RLDRAM II devices. Figure 2–9 on page 2–14 ...

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... Optional non_dqs_capture_clk Fed-Back Clock PLL (Note 1) RLDRAM II Controller clk altddio write_clk altddio Address & Command addr_cmd_clk Registers (Note 2) Stratix II DLL shows a testbench and an example design. MegaCore Version 9.1 rldramii_qk rldramii_clk_n rldramii_clk RLDRAM II rldramii_a_0[] rldramii_ba_0[] rldramii_cs_n_0 rldramii_ref_n_0 rldramii_we_n_0 Altera Corporation November 2009 ...

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... Table 2–2: <top-level name> is the name of the Quartus II project top-level entity. <variation name> is the variation name. Altera does not provide a memory simulation model. You must download one or use your own. MegaCore Version 9.1 RLDRAM II Controller MegaCore Function User Guide Functional Description ...

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... Sets rldramii_qk[] non-global signal in DQS capture mode Add Hold Relationship and Setup Relationship to all I/O ports. Initialization Writes Reads Refreshes On-die termination (ODT) Impedance matching resistor DLL enable RLDRAM II configuration shows the initialization sequence. MegaCore Version 9.1 “Simulate the Altera Corporation November 2009 ...

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... RLDRAM II t functionality means that the write request is decoupled from the write data. Figure 2–12 interface. In this example, the memory burst length is set to eight beats. The RLDRAM II device is setup with a t (configuration two). Altera Corporation November 2009 MRS RF0 RF1 0 1 2,048 ...

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... RLDRAM II Controller MegaCore Function User Guide A01 A23A45 A67 B01 B23 B45 B67 C01 C23 C45 shows the transactions at the local interface are separated by shows an example of a write following a read at a CIO MegaCore Version 9.1 C67 six-clock cycles RC Altera Corporation November 2009 ...

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... DQS delay circuitry. In non-DQS mode the read data, rldramii_dq[] or rldramii_q[], and the QVLD signals, rldramii_qvld[], are captured using an external capture clock. Altera Corporation November 2009 ...

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... RLDRAM II Controller MegaCore Function User Guide shows an example of a read at an SIO RLDRAM II interface. of six-clock cycles (configuration A01 A23 A45 A67 B01 B23 B45 B67 C01 C23C45 C67 shows an example of a read following a write at a CIO MegaCore Version 9.1 C67 six-clock cycles RC Altera Corporation November 2009 ...

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... You must correctly insert the refresh request and ensure that the t parameter is not violated. You can issue single or ganged refreshes. For ganged refreshes assert local_refresh_req for X clock cycles, where X is the number of refreshes that you require. Figure 2–16 Altera Corporation November 2009 ...

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... RLDRAM II Controller MegaCore Function User Guide shows the system signals. Width Direction (Bits) Input System clock for the control logic and datapath. Input Shifted clock that center aligns write data to the memory. MegaCore Version 9 Description Altera Corporation November 2009 ...

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... Table 2–3. System Signals (Part Name 1 addr_cmd_clk 6 dqs_delay_ctrl[] 1 non_dqs_capture_clk 1 reset_clk_n 1 reset_addr_cmd_clk_n Altera Corporation November 2009 Width Direction (Bits) Input Address and command output register clock. The frequency must be the same as the system clock, write_clk In addition, when there is a separate address and command clock phase, no ...

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... Reset input for logic on the address and command clock domain. The reset_addr_cmd_clk_n asserted asynchronously but must be deasserted synchronous to the rising edge of the address and command clock. MegaCore Version 9.1 Description addr_cmd_clk clock clk , and the write clock, , frequencies. can be reset_clk_n can be Altera Corporation November 2009 ...

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... The number of local_dm[] RLDRAM II devices attached to the memory interface × local_read_req 1 local_refresh_req Altera Corporation November 2009 Width Direction (Bits) Input Reset input for logic on the capture clock domain. In DQS mode, the capture clock domain is mode DQS mode, each reset_read_clk_n[] with the corresponding clock domain ...

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... Direction Bidirectional Memory data bus. CIO devices only. Bidirectional In DQS mode, the memory data strobe signal that captures read data into the Altera device; in non-DQS mode, the RLDRAM II controller does not use Input Memory read data bus. SIO devices only. ...

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... Note to Table 2–5: (1) The default signal is <signal>_0. When you specify additional address and command busses, both <signal>_0 and <signal>_1 are present. Altera Corporation November 2009 Direction Input Read data valid flag. Output Memory address signals. Output Memory bank address signals. ...

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... The control_qvld[] functionality as local_rdata_valid[] Output The captured read data (same as local_rdata[] 3–5). MegaCore Version 9.1 Description is asserted. is asserted when the or rldramii_dq control_wdata_valid control_qvld[] control_rdata[] signal has the same . ). “Step 1: Altera Corporation November 2009 ...

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... Number 80,000 initialization clock cycles Enable on-die On or off termination Altera Corporation November 2009 shows the memory type parameters. Units – A part number for a particular memory device. Choosing an entry sets many of the parameters in the wizard to the correct value for the specified part. You can add your own devices to this list by editing the memory_types ...

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... HardCopy II devices. When turned off altddio outputs. – The number of RLDRAM II clock output pairs generated in the datapath. When you turn on Use dedicated clock outputs, only values are valid. MegaCore Version 9.1 Description outputs generate the clock Altera Corporation November 2009 ...

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... Use migratable byte On or off groups Fedback PLL phase ± 180 offset Altera Corporation November 2009 shows the pipeline options. Description When you choose the wizard inserts pipeline registers between the memory controller and the command and address output registers and the write data output registers. These registers may help to achieve the required performance at higher frequencies ...

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... Enter the pin loading to match your board and memory devices. Enter the pin loading to match your board and memory devices. Enter the pin loading to match your board and memory devices. shows the example design settings. Description MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Verification Simulation Environment Altera has carried out extensive functional tests using industry-standard models to ensure the functionality of the RLDRAM II controller. In addition, Altera has carried out a wide variety of gate-level tests on the RLDRAM II controller to verify the post-compilation functionality of the controller. Hardware Testing Table 2–16 hardware tested the RLDRAM II controller. Table 2– ...

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... MegaCore Verification 2–34 RLDRAM II Controller MegaCore Function User Guide MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Contains scripts that generate an instance-specific Tcl script for each instance of the RLDRAM II Controller in various Altera devices. dat Contains a data file for each Altera device combination that is used by the Tcl script to generate the instance-specific Tcl script. doc Contains the documentation for the RLDRAM II Controller MegaCore function. ...

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... If you obtain a license for the RLDRAM II controller, you must set up licensing. Generate a programming file for the Altera device(s) on your board. “Create a New Quartus II Project” on page 3–3 “Launch IP Toolbench” on page 3–4 MegaCore Version 9.1 ...

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... Constraints” on page 3–7 “Step 3: Set Up Simulation” on page 3–8 “Step 4: Generate” on page 3–8 Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. Choose New Project Wizard (File menu). ...

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... New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>. 1 The <variation name> must be a different name from the project name and the top-level design entity name. Click Next to launch IP Toolbench. MegaCore Version 9.1 Altera Corporation November 2009 ...

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... For more information on timing parameters, refer to page For more information on project settings, refer to page Altera Corporation November 2009 2–28. Click Step 1: Parameterize in IP Toolbench . Choose the memory type. a. Choose the memory device. 1 You can add your own memory devices to this list by editing the memory_types ...

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... RLDRAM II Controller Walkthrough 10. Altera recommends that you turn on Automatically apply 1 11. Ensure Update the example design file that instantiates the 1 12. Turn off Update example design system PLL, if you have edited the 1 13. The constraints script automatically detects the hierarchy of your ...

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... IP Toolbench uses a prefix (for example, rldramii_) for the names of 15. Enter the pin loading for the FPGA pins. 16. Click Finish. Step 2: Constraints To choose the constraints for your device, follow these steps Altera Corporation November 2009 example_top my_system System my_sub_system Subystem ...

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... Some third-party synthesis tools can use a netlist that contains only the structure of the MegaCore function, but not detailed logic, to optimize performance of the design that contains the MegaCore function. If your synthesis tool supports this feature, turn on Generate netlist. Click OK. MegaCore Version 9.1 Altera Corporation November 2009 ...

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... Datapath. Altera Corporation November 2009 describes the generated files and other files that may be in your Note (1), (2), (3) A MegaCore function variation file, which defines a VHDL or Verilog HDL description of the custom MegaCore function ...

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... Quartus II compiler. Generally, a single .qip file is generated for each MegaCore function or system in the Quartus II compiler. 3–11), edit the PLL(s), and compile (refer to 3–14). MegaCore Version 9.1 Description “Simulate the Example “Compile Altera Corporation November 2009 ...

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... HDL testbench for your example design, which is in the testbench directory in your project directory. f For more information on the testbench, refer to page You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. To simulate the example design with the ModelSim ...

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... NativeLink Settings, select Compile Test Bench and click Test Benches. Click New. Enter a name for the Test bench name. Enter the name of the automatically generated testbench, <project name>_tb, in Test bench entity. Enter the name of the top-level instance in Instance. MegaCore Version 9.1 r Simulating Altera IP in Altera Corporation November 2009 ...

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... For more information on the altpll megafunction, refer to the Quartus II Help or click Documentation in the ALTPLL MegaWizard Plug-In. Altera Corporation November 2009 of the RLDRAM II model and the testbench, <project name>_tb, click OK and click Add. EDA RTL Simulation. If you turn off Enable DQS mode, IP Toolbench generates a second PLL— ...

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... Expand Analysis and Synthesis Settings in the category list. Select Speed in Optimization Technique. Expand Fitter Settings. Turn on Optimize Hold Timing and select All Paths. Turn on Fast-corner timing. Click OK. Re-compile the example design by choosing Start Compilation (Processing menu). MegaCore Version 9.1 3–6). Altera Corporation November 2009 ...

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... After you have compiled the example design, you can perform gate-level simulation (refer to Device program your targeted Altera device to verify the example design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the RLDRAM II Controller MegaCore function before you obtain a license. ...

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... After you obtain a license for RLDRAM II controller, you can request a license file from the Altera web site at install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. ...

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... Product literature FTP site Note to table: (1) Altera Corporation Additional Information Changes Made Information Type www.altera.com/mysupport/ www.altera.com/training/ custrain@altera.com www.altera.com/literature ftp.altera.com You can also contact your local Altera sales office or sales representative. MegaCore Version 9.1 RLDRAM II Controller MegaCore Function User Guide Contact Note (1) i ...

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... The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. ii RLDRAM II Controller MegaCore Function User Guide Meaning , , and Active-low signals are denoted by suffix tdi input. . resetn c:\qdesigns\tutorial\chiptrip.gdf ). TRI MegaCore Version 9.1 . For and logic function SUBDESIGN Altera Corporation ...