IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 7

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Contact
Information
Altera Corporation
Solution Status
This issue will be fixed in a future version of the Quartus II software.
Editing the Custom Variation (non-DQS Mode)
When you generate a non-DQS mode custom variation with wide
databus widths, you may encounter one of the following characteristics
when you try to edit the custom variation:
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■
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Affected Configurations
This issue affects non-DQS mode designs only.
Design Impact
There is no design impact, if you implement the workaround.
Workaround
Use one of the following workarounds:
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Solution Status
This issue will be fixed in a future version of the RLDRAM II controller.
For more information, contact Altera's mySupport website at
www.altera.com/mysupport and click Create New Service Request.
Choose the Product Related Request form.
IP Toolbench does not reload
IP Toolbench reloads, but the databus width and constraints are set
to the default for the selected RLDRAM II device
IP Toolbench reloads, but the databus width is set to the default value
for the selected RLDRAM II device and the constraints floorplan
shows no chosen byte groups
If IP Toolbench does not reload, you must regenerate a new custom
variation and re-enter your parameters
If IP Toolbench reloads, but the databus width and constraints are set
to the default, reselect the databus width and rechoose the byte
groups in the constraints floorplan
If IP Toolbench reloads, but the databus width is set to the default
and the constraints floorplan shows no byte groups, reselect the
databus width and rechoose the byte groups in the constraints
floorplan
RLDRAM II Controller MegaCore Function v7.1 Errata Sheet
Contact Information
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