IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 171

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Frame Buffer
Table 6–12. Frame Buffer Signals (Part 2 of 3)
January 2011 Altera Corporation
read_master_av_burstcount
read_master_av_clock
read_master_av_read
read_master_av_readdata
read_master_av_readdatavalid
read_master_av_reset
read_master_av_waitrequest
reader_control_av_chipselect
reader_control_av_readdata
reader_control_av_write
reader_control_av_writedata
write_master_av_address
write_master_av_burstcount
write_master_av_clock
write_master_av_reset
write_master_av_waitrequest
write_master_av_write
write_master_av_writedata
Signal
Direction
Out
In
Out
In
In
In
In
In
Out
In
In
Out
Out
In
In
In
Out
Out
read_master port Avalon-MM burstcount signal. Specifies the
number of transfers in each burst.
read_master port The clock signal. The interface operates on the
rising edge of the clock signal.
read_master port Avalon-MM read signal. Asserted to indicate
read requests from the master to the system interconnect fabric.
read_master port Avalon-MM readdata bus. These input lines
carry data for read transfers.
read_master port Avalon-MM readdatavalid signal. This
signal is asserted by the system interconnect fabric when the
requested read data has arrived.
read_master port reset signal. The interface is reset
asynchronously when this signal is asserted high and must be de-
asserted synchronously with respect to the rising edge of the
clock signal.
read_master port Avalon-MM waitrequest signal. Asserted by
the system interconnect fabric to cause the master port to
wait.
reader_control slave port Avalon-MM chipselect signal. The
reader_control port ignores all other signals unless this signal
is asserted.
reader_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
reader_control slave port Avalon-MM write signal. When this
signal is asserted, the reader_control port accepts new data
from the writedata bus.
reader_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
write_master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
write_master port Avalon-MM burstcount signal. Specifies
the number of transfers in each burst.
write_master port clock signal. The interface operates on the
rising edge of the clock signal.
write_master port reset signal. The interface is reset
asynchronously when this signal is asserted high and must be de-
asserted synchronously with respect to the rising edge of the
clock signal.
write_master port Avalon-MM waitrequest signal. Asserted
by the system interconnect fabric to cause the master port to wait.
write_master port Avalon-MM write signal. Asserted to
indicate write requests from the master to the system interconnect
fabric.
write_master port Avalon-MM writedata bus. These output
lines carry data for write transfers.
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(1)
(1)
Description
(2)
Video and Image Processing Suite User Guide
(1)
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