IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 96

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–16
Video and Image Processing Suite User Guide
Overflow
Timing Constraints
Active Format Description Extractor
A Clocked Video Output MegaCore function can take in the locked PLL clock and the
SOF signal and align the output video to these signals. This produces an output video
frame that is synchronized to the incoming video frame. For more information, refer
to the description of the Clocked Video Output MegaCore function.
Moving between the domain of clocked video and the flow controlled world of
Avalon-ST Video can cause problems if the flow controlled world does not accept data
at a rate fast enough to satisfy the demands of the incoming clocked video.
The Clocked Video Input MegaCore function contains a FIFO that, when set to a large
enough value, can accommodate any bursts in the flow data, as long as the input rate
of the upstream Avalon-ST Video components is equal to or higher than that of the
incoming clocked video.
If this is not the case, the FIFO overflows. If overflow occurs, the MegaCore function
outputs an early endofpacket signal to complete the current frame. It then waits for
the next start of frame (or field) before re-synchronizing to the incoming clocked
video and beginning to output data again.
The overflow is recorded in bit [9] of the Status register. This bit is sticky, and if an
overflow occurs, stays at 1 until the bit is cleared by writing a 0 to it.
In addition to the overflow bit, the current level of the FIFO can be read from the Used
Words register.
To constrain the Clocked Video Output MegaCore function correctly, add the
following file to your Quartus II project:
When you apply the SDC file, you may see some warning messages in a format as
follows:
■
■
These warnings are expected, because in certain configurations the Quartus II
software optimizes unused registers and they no longer remain in your design.
The AFD Extractor is an example of how to write a core to handle ancillary packets. It
is available in the following directory:
<install_dir>\ip\clocked_video_output\lib\afd_example
When the output of the Clocked Video Input MegaCore function is connected to the
input of the AFD Extractor, the AFD Extractor removes any ancillary data packets
from the stream and checks the DID and secondary DID (SDID) of the ancillary
packets contained within each ancillary data packet. If the packet is an AFD packet
(DID = 0x41, SDID = 0x5), the extractor places the contents of the ancillary packet into
the AFD Extractor register map.
Warning: At least one of the filters had some problems and could not be matched.
Warning: * could not be matched with a keeper.
<install_dir>\ip\clocked_video_input\lib\alt_vip_cvi.sdc
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Clocked Video Input