JN5139/001,515 NXP Semiconductors, JN5139/001,515 Datasheet - Page 10

• Manufacturer Part Number: JN5139/001,515
• Description: IC MCU 32BIT 56QFN
• Manufacturer: NXP Semiconductors

Specifications of JN5139/001,515

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2 Pin Descriptions
2.2.1 Power Supplies
The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1
is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the
digital circuitry; it should be decoupled to ground. A 10uF tantalum capacitor is required at the common ground star
point of analogue and digital supplies. Decoupling pins for the internal 1.8V regulators are provided which require a
100nF capacitor located as close to the device as practical. VB_VCO, VB_RF, VB_A and VB_SYN should be
decoupled to analogue ground, while VB_MEM, VB_DIG1 and VB_DIG2 should be decoupled to ground. VB_SYN
and VB_RF also require an additional 47pF capacitor. See also Appendix B for connection details.
VSSA is the analogue ground, connected to the paddle of the device, while VSSS, VSS1, VSS2, VSS3 are digital
ground pins. All grounds should be connected to a ground plane.
2.2.2 Reset
RESETN is a bi-directional active low reset pin that is connected to a 40kΩ internal pull-up resistor. It may be pulled
low by an external circuit, or can be driven low by the JN5139 if an internal reset is generated. Typically, it will be
used to provide a system reset signal. Refer to section 6.2, External Reset, for more details.
2.2.3 16MHz System Clock
A crystal connected between XTALIN and XTALOUT drives the system clock. A capacitor to analogue ground is
required on each of these pins. Refer to section 5.1 16MHz System Clock / Crystal Oscillator for more details.
2.2.4 Radio
A 200Ω balanced antenna (such as a printed circuit antenna) can be connected directly to the radio interface pins
RFM and RFP.
A single-ended 50Ω antenna such as a ceramic type or SMA connector for an external antenna requires the addition
of a 200/50Ω 2.45GHz balun transformer connected to the antenna pins. The balun differential port should be
connected to the antenna port with 200Ω balanced controlled impedance track. A 50Ω controlled impedance track
should be used to connect the unbalanced port of the balun to the antenna to ensure good impedance matching and
reduce losses and reflections.
A simple external loop filter circuit consisting of two capacitors and a resistor is connected to VCOTUNE. Refer to
section 8.1 Radio for more details.
An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and
references within the radio.
2.2.5 Analogue Peripherals
Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use
either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to
analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference.
There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the
JN5139 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in
Figure 3: Analogue I/O Cell
In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state.
In sleep, the ADC and DACs are off, with the DAC outputs in high impedance state. The comparators may optionally
be used as a wakeup source.
Unused ADC and comparator inputs should be left unconnected.
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JN-DS-JN5139 1v9
© NXP Laboratories UK 2010