DS3105DK Maxim Integrated Products, DS3105DK Datasheet - Page 13

• Manufacturer Part Number: DS3105DK
• Description: Power Management Modules & Development Tools Demo Kit for DS3105 Demo Kit for DS3105
• Manufacturer: Maxim Integrated Products

Specifications of DS3105DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6
In the DS3105, the T4 APLL is always connected to the output of the T0 DPLL.
The Input Freq field configures the frequency of the T4 APLL DFS (refer to the DS3105 data sheet for details). The
APLL output frequency is always four times the input frequency. When the Input Freq field is changed, the Output
Freq field changes to match, and all the T4 options in the output clock combo boxes also change to frequencies
derived from the new T4 APLL frequency. These changes match what happens in the DS3105.
Whenever the T4 APLL DFS is configured for programmable DFS operation (see Section 4.10) the Input Freq and
Output Freq fields specify their frequencies with a “P” prefix to indicate that programmable DFS mode is enabled
for the T4 APLL DFS.
Table 4-5. Mapping Between T4 APLL Software Fields and DS3105 Register Fields
4.7
The fields in the OUTPUT CLOCKS box configure the DS3105’s output clocks. The DIG1 and DIG2 fields
configure the Digital1 and Digital2 frequency options for OC3 and OC6 (refer to the DS3105 data sheet for details).
The OC3 and OC6 fields specify the output frequencies for outputs OC3 and OC6, respectively. Note that when the
T0 APLL setting is changed, the frequencies of all the T0 options in the OC3 and OC6 fields automatically change
to frequencies derived from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the
frequencies of all the T4 options in the OC3 and OC6 fields automatically change to frequencies derived from the
new T4 APLL frequency. These changes match what happens in the DS3105.
Whenever the T0 APLL DFS, T4 APLL DFS, or T0 APLL2 DFS are configured for programmable DFS operation
(see Section 4.10) the T0, T4 and T02 options, respectively, in the OC3 and OC6 fields change to frequencies
derived from the programmable DFS settings. These options all have a “P” prefix, for example, “PT0” or “PT4” to
indicate that they are controlled by the programmable DFS mode. Similarly, whenever the DIG1 DFS or the DIG2
DFS are configured for programmable DFS operation, the DIG1 and DIG2 fields change to display the
programmable DFS frequency with a “P” prefix.
FSYNC is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be
inverted. MFSYNC is a 2kHz output that can be similarly configured.
Table 4-6. Mapping Between Output Clock Software Fields and DS3105 Register Fields
Rev: 012808
_________________________________________________________________________________________DS3105DK
T4 APLL
Output Clocks
SOFTWARE FIELD
SOFTWARE FIELD
Output Freq
Input Freq
OC3 and OC6
MFSYNC
FSYNC
DIG1
DIG2
OCR4:MFSEN, FSCR1:2KPUL, FSCR1:2KINV
MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF
OCR4:FSEN, FSCR1:8KPUL, FSCR1:8KINV
Derived by software from Input Freq
DS3105 REGISTER FIELDS
MCR6:DIG1SS, MCR7:DIG1F
DS3105 REGISTER FIELDS
T0CR1:T0FT4
OCR2 and OCR3
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