DS3105 Maxim Integrated Products, DS3105 Datasheet
DS3105
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DS3105 Summary of contents
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... GENERAL DESCRIPTION The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs and performs automatic hitless reference switching if the primary reference fails. The highly programmable ...
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... Input to Output (Manual) Phase Adjustment ................................................................................ 28 7.7.9 Phase Recalibration ..................................................................................................................... 28 7.7.10 Frequency and Phase Measurement ........................................................................................... 29 7.7.11 Input Jitter Tolerance.................................................................................................................... 30 7.7.12 Jitter Transfer ............................................................................................................................... 30 7.7.13 Output Jitter and Wander ............................................................................................................. 30 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. TABLE OF CONTENTS 2 of 110 DS3105 ...
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... JTAG Interface Timing............................................................................................................................. 102 10.6 Reset Pin Timing ..................................................................................................................................... 103 11 PIN ASSIGNMENTS ......................................................................................................................................... 104 12 MECHANICAL INFORMATION ........................................................................................................................ 106 13 ACRONYMS AND ABBREVIATIONS............................................................................................................... 108 14 DATA SHEET REVISION HISTORY ................................................................................................................ 109 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... Figure 10-5. JTAG Timing Diagram......................................................................................................................... 102 Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 103 Figure 11-1. Pin Assignment Diagram..................................................................................................................... 105 Figure 12-1. LQFP Mechanical Dimensions............................................................................................................ 106 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. LIST OF FIGURES 4 of 110 DS3105 ...
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... Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 104 Table 12-1. LQFP Thermal Properties, Natural Convection.................................................................................... 107 Table 12-2. LQFP Theta-JA (θ ) vs. Airflow ........................................................................................................... 107 JA Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. LIST OF TABLES 5 of 110 DS3105 ...
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... SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000 GR-1244-CORE Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... HW Control and Status Pins 7 of 110 19.44 MHz To SONET/SDH framers, 155.52MHz differential Clock Multiplying APLLs, etc. on the Line Card Output Clock Synthesizer and OC3 Selector OC6 POS/NEG (Muxes, FSYNC 7 DFS Blocks, MFSYNC 3 APLLs, Output Dividers) Master Clock Generator REFCLK Local Oscillator DS3105 ...
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... In the DS3105 the T4 DPLL can only be used as an optional clock monitoring block. T4 can be directed to lock to an input clock and can measure the frequency of the input clock or the phase difference between two input clocks. ...
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... Custom clock rates also available: any multiple of 2 kHz up to 77.76 MHz and any multiple of 8 kHz up to 311.04MHz • All outputs have < peak-to-peak output jitter; outputs from APLLs have < 0.5 ns peak-to-peak Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... Operates from a single external 12.800 MHz local oscillator (XO or TCXO) • SPI serial microprocessor interface • Four general-purpose I/O pins • Register set can be write-protected Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... This pin is not used for the external frame sync signal. This pin is the external frame sync signal associated with IC4 or IC6 depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Table 10-5, Table 10 110 Figure 10-2. Figure 10-2. Table Table 7-18. , Figure 10-1 and Figure 10-3. DS3105 7-18. ...
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... Preliminary. Subject to Change Without Notice. :EXTSW when RST goes high. After RST goes high this pin can be used to select register. This gives the system a very fast indication of the failure of the current 12 of 110 Table Table Table Table Table INTCR register. Polarity can be active-high or DS3105 7-18. 7-18. 7-17. 7-17. 7-17. ...
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... AVDD_PLL3 P AVSS_PLL3 P Return for T4 APLL. Power Supply for T0 APLL2. 1.8V ±10%. AVDD_PLL4 P AVSS_PLL4 P Return for T0 APLL2. Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. 10.4 for timing specifications. 7-4. 10.5 for timing specifications 110 DS3105 ...
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... LVDS/LVPECL differential signal compatible DIFF P = power-supply pin All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality. Note 3: Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... FUNCTIONAL DESCRIPTION 7.1 Overview The DS3105 has five input clocks and two output clocks. There are two separate DPLLs in the device: the high- performance T0 DPLL and the simpler T4 DPLL. The T0 DPLL can generate output clocks, the T4 DPLL can be used to monitor inputs for frequency and phase. See Three of the input clock pins are single-ended and can accept clock signals from 2 kHz to 125 MHz ...
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... The adjust can be from –771 ppm to +514 ppm in 0.0196229 ppm (i.e. ~0.02 ppm) steps. 7.4 Input Clock Configuration The DS3105 has five input clocks, IC3 to IC6 and IC9. including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time 30% of the clock period, whichever is smaller ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Default Frequency (1) 8 kHz (1) 8 kHz (2) 19.44 MHz (2) 19.44 MHz (1) 19.44 MHz ICR registers. The DIVN and LOCK8K bits of these Table 7-2. ICR register description). The alternate frequencies are included to support ICR 17 of 110 DS3105 register. ICR ...
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... Frequency Monitoring The DS3105 monitors the frequency of each input clock and invalidates any clock whose frequency is more than 10,000 ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit. The frequency range measurement uses the internal 204.8 MHz master clock as the frequency reference. ...
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... PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If NALOL=1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an interrupt request if enabled. Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
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... Preliminary. Subject to Change Without Notice. (IPR2 MCR11 MCR11 register, these registers indicate the highest priority input clocks for PTAB1 register). (The selection algorithm always switches to the 20 of 110 DS3105 , IPR3 and IPR5). Each of these registers register, the IPR registers specify the VALSR1 and VALSR2 registers ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. register and the T4FORCE field in the register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced 110 DS3105 MCR4 register provide a way to force a MCR4 register can be used to select the ...
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... APLL DFS T0CR1:T0FREQ[2:0] T0 APLL2 Output DFS APLL2 FSYNC DFS FSCR2:INDEP OUTPUT DFS 22 of 110 2K8K DIG1 DIG2 OC3, OC6 T4 APLL Output APLL Dividers OCRm:OFREQn[3:0] OCR5:AOFn T0 APLL Output APLL Dividers T0 APLL Output Dividers FSYNC, 2 MFSYNC OCR4:FSEN, MFSEN FSCR1:8KINV, 2KINV FSCR1:8KPOL, 2KPOL DS3105 ...
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... MCR1 register. MSR2 is set, which can cause an interrupt request if MCLK1 PHLKTO ISR register), invalidating the input (ICn bit goes low 23 of 110 DS3105 OPSTATE register. and MCLK2 (see section 7.3). The state register) for the DPLL to lock to the PHLKTO PHLKTO register must be ...
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... OR out of lock >100s) AND no valid input clock available all input clocks evaluated at least one input valid VALSR 24 of 110 DS3105 selected reference invalid > 2s AND no valid input clock available Holdover select ref (010) registers and the ISR registers) ...
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... FRUNHO=1 in MCR3), the holdover frequency is set to an internally MSR4 (latched status). If the T0 DPLL must enter holdover before the 110 ISR registers), invalidating the input (ICn bit PHLKTO register must be FREQ2 DS3105 VALSR PHLKTO and ...
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... When AUTOBW=1, the T0 T4CR2 register. The reset default damping factors for T0ABW and T0LBW Damping Factor Gain Peak, dB 1.2 0.4 2.5 0.2 5 0.1 1.2 0.4 2.5 0.2 5 0.1 10 0.06 1.2 0.4 2.5 0.2 5 0.1 10 0. 110 DS3105 and MCLK2 (see section 7.3). When registers for various values from T0CR2 register, while the damping registers). See Table 7-4. ...
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... T4 DPLL. The reset default register. The range of the MCPD— PHLIM1 register. The fine phase limit is register. The coarse phase limit is DLIMIT3 register. The hard limit for the T0 register also has the SOFTLIM field to OPSTATE register. When the T4 DS3105 ...
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... PHLIM1 register. When this detector is enabled the register and requests an interrupt if enabled. OFFSET registers can be used to adjust the phase of OFFSET registers are written during the recalibration process, the 28 of 110 DS3105 OPSTATE register, which sets the PBOFF OFFSET registers, and then ...
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... T0 path continues to lock to the T0 selected reference in the manner specified in the corresponding Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Table 7-5 for more details. (While T0CR1:T4MT0=1 the 29 of 110 DS3105 FREQ2 and FREQ3. PHASE1 and PHASE2. This ICR ...
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... DIVN 8 kHz DIRECT 8 kHz same as the T4 forced DIRECT ref input frequency same as the T4 forced DIRECT ref input frequency 30 of 110 DS3105 Frequency of the T0 Selected Ref for T4MT0 Phase Measurement 8 kHz 8 kHz 8 kHz 8 kHz same as the T0 selected (1) ref input frequency same as the T0 selected ...
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... The frequency of output clocks OC3 and OC6 is a function of the settings used to configure the components of the T0 PLL paths. These components are shown in the detailed block diagram of The DS3105 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8 MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS output is a coding of the clock output phase which is used by a special circuit to determine where to put the edges of the output clock between the clock edges of the master clock ...
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... AOFn bits in the Table 7-14 also indicates the expected jitter amplitude for each frequency. Jitter, pk-pk nsec, Frequency, MHz typical 2.048 < 1 4.096 < 1 8.192 < 1 16.384 < 1 1.544 < 1 3.088 < 1 6.176 < 1 12.352 < 110 DS3105 and Table 7-8, respectively. OCR5 register. ...
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... T0FREQ[2:0] Setting Output Jitter, in T0CR1 pk-pk, ns, typ 000 < 0.5 001 < 0.5 010 < 0.5 011 < 0.5 100 < 0.5 101 < 0.5 110 < 0.5 111 < 0.5 DS3105 APLL / 64 -- 4.86 4.296 -- 2.796 2.5 2.316 2.048 1.92 -- 1.578 1.544 1.536 ...
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... XXX 0101 XXX 0110 XXX 0111 XXX 1000 XXX 1001 XXX 1010 XXX 1011 XXX 1100 XXX XXXX 000 XXXX 001 XXXX 010 XXXX 100 XXXX 110 XXXX 111 DS3105 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 ...
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... DS1 16 x DS1 16 x DS1 GbE ÷ 6.312 4 x 6.312 6.312 24 x DS1 24 x DS1 35 of 110 DS3105 Jitter (typ) OFREQn rms T4FREQ (ps) 2 kHz 100 8 kHz 100 APLL/64 50 DIG1,DIG2 100 ...
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... DS1 16 x DS1 4 x 6312 kHz 4 x 6312 kHz GbE ÷ 16 GbE ÷ DS1 24 x DS1 77.76 GbE ÷ 16 77. 110 DS3105 Jitter (typ) OFREQn rms T4FREQ (ps) 77.76 APLL/ APLL APLL/5 50 DS3 ...
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... OFREQ6 SRC 0000 --- 1111 T4 1110 T4 0110 T0 0111 T0 1000 T0 1001 T0 1010 T0 0011 T0 O6F[2:0] OCR2. APLL =001 OFREQ3 SRC X 0000 --- 1101 T4 FALSE 1101 T4 0111 T0 TRUE 0111 T0 X 1111 T4 X 1110 T4 X 0110 T0 X 0111 T0 X 1000 T0 X 1001 T0 X 1010 110 DS3105 ...
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... The higher-speed clock from each timing card is connected to a regular input clock pin on the DS3105, such as IC3 or IC4, while the frame sync signal is connected to a SYNCn input pin on the DS3105, such as SYNC1 or SYNC2. The DS3105 locks to the higher-speed clock from one of the timing cards and samples the frame sync signal on the associated SYNCn pin ...
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... SYNCn’s new phase alignment, causing a sudden phase movement on the output clocks. System software can avoid this sudden phase movement on the output clocks by responding to the FSMON Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 IER3 register. ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. External Frame Sync Source SYNC1 SYNC2 SYNC1 SYNC2 SYNC1 SYNC2 SYNC3 FSCR2 7.9.4 is only performed on the selected SYNCn input pin 110 IER3 register. register. PHASE1[1:0] is associated with DS3105 ...
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... Burst Writes. See Figure followed by the first data byte to be written. The DS3105 receives the first data byte on SDI, writes it to the specified register, increments its internal address register, and prepares to receive the next data byte. If the master continues to transmit, the DS3105 continues to write the data received and increment its address counter. After the address counter reaches 3FFFh it rolls over to address 0000h and continues to increment ...
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... Preliminary. Subject to Change Without Notice. Figure 10-4 for AC timing specifications for the SPI interface. MSB CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES) Data Byte 0 (single-byte) 0 (single-byte) Data Byte Data Byte N 1 (burst) 1 (burst) Data Byte 1 Data Byte 110 LSB DS3105 ...
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... Initialization After power-up or reset, a series of writes must be done to the DS3105 to tune it for optimal performance. This series of writes is called the initialization script. Each die revision of the DS3105 has a different initialization script. The latest initialization scripts can be obtained by downloading from the DS3105 web page, ic.com/DS3105 emailing telecom.support@dalsemi.com. Important: System software must wait at least 100µ ...
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... REGISTER DESCRIPTIONS The DS3105 has an overall address range from 000h to 1FFh. each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “--“ are reserved and must be written with 0. Writing other values to these registers may put the device in a factory test mode resulting in undefined operation. Bits labeled “ ...
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... T0STATE[2:0] SELREF[3:0] REF2[3:0] IC4 IC3 -- -- -- -- -- -- ACT3 -- -- ACT5 -- -- ACT9 -- -- -- PRI3[3:0] PRI5[3:0] PRI9[3:0] FREQ[3:0] FREQ[3:0] FREQ[3:0] FREQ[3:0] FREQ[3:0] IC4 IC3 -- -- -- -- -- T0STATE[2:0] T0FORCE[3:0] EFSEN SONSDH -- T4FORCE[3: IC6SF -- -- -- -- -- -- -- OC6SF LIMINT -- -- -- -- -- HARDLIM[9:8] -- IC4 IC3 -- -- -- -- -- -- DS3105 Bit IC9 -- -- IC9 LOCK3 LOCK5 LOCK9 -- -- IC9 REVERT -- -- -- -- -- IC9 -- ...
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... Bit 3 Bit 2 Bit 1 PBOEN -- -- -- -- -- -- -- -- AOF3 -- -- -- LB0D[1: LB1D[1: LB2D[1: LB3D[1:0] OFREQ3[3: T4FREQ[3:0] T0FREQ[2: T4BW[1:0] RSV2 T0LBW[2:0] RSV2 T0ABW[2:0] -- DAMP[2:0] -- DAMP[2:0] -- PD2G[2:0] -- PD2G[2:0] GPIO3O GPIO2O GPIO4 GPIO3 GPIO2 PBOFF[5:0] -- FINELIM[2:0] COARSELIM[3:0] -- PHLKTO[5:0] 8KINV 8KPUL 2KINV PHASE2[1:0] PHASE1[1:0] DS3105 Bit GPIO1O GPIO1 2KPUL ...
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... DPLL State Output Clock Configuration Frame/Multiframe Sync Configuration Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 6 Bit 5 Bit 4 MONLIM[2: PROT[7: 110 Bit 3 Bit 2 Bit 1 SOURCE[3:0] LOS GPO OD DS3105 Bit 0 POL ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 ID[7: Bit 5 Bit 4 Bit 3 ID[15: ID1 register description. Bit 5 Bit 4 Bit 3 REV[7: 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit ...
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... Bit 1: Leave set to zero (test control). Bit 0: Leave set to zero (test control). Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 — 110 DS3105 Bit 2 Bit 1 Bit 0 8KPOL ...
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... Bit 5 Bit 4 Bit IER2 register. See section Bit 5 Bit 4 Bit FREQ1 50 of 110 DS3105 Bit 2 Bit 1 Bit 0 IC3 -- 1 1 IER1 register. See section Bit 2 Bit 1 Bit IC9 0 0 OPSTATE register. See IER2 register. SRFAIL VALSR VALSR2 7 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 T0SOFT T4SOFT -- 110 DS3105 Bit 2 Bit 1 Bit IER3 register. See section 7.9. Bit 2 Bit 1 Bit 0 T0STATE[2: DLIMIT3 register. See DLIMIT3 register. See -- ...
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... T0 DPLL. When VALCR1 or VALCR2 register. When the T0 DPLL is in non-revertive mode 52 of 110 Bit 2 Bit 1 SELREF[3: VALCR1 or VALCR2 register. When DS3105 Bit 0 0 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 REF3[3: 110 Bit 2 Bit 1 REF2[3: MCR11 register, this field indicates the third MCR11 register, this field indicates the DS3105 Bit 0 0 VALCR1 or VALCR1 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 FREQ[7: Bit 5 Bit 4 Bit 3 FREQ[15: 110 DS3105 Bit 2 Bit 1 Bit MCR11 register, FREQ indicates MCR9 Bit 2 Bit 1 Bit ...
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... Bit 2 Bit 1 Bit 0 IC3 -- 0 0 Bit 2 Bit 1 Bit VALSR1 but for the IC9 clock. Bit 2 Bit 1 Bit 0 -- ACT3 LOCK3 0 1 register (where ‘x’ in ‘LBxU’ is specified in VALSR1 register, invalidating the IC4 PHLKTO register (default = 100 DS3105 -- 0 IC9 0 0 ...
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... IC5 and IC6. Bit 5 Bit 4 Bit ISR2 register, but for input clock IC9. Bit 5 Bit 4 Bit 3 MRAA -- -- 110 DS3105 Bit 2 Bit 1 Bit 0 -- ACT5 LOCK5 Bit 2 Bit 1 Bit 0 -- ACT9 LOCK9 Bit 2 Bit 1 Bit 0 ...
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... IPR2 but for input clocks IC5 and IC6. Bit 5 Bit IPR2 but for input clock IC9 110 Bit 3 Bit 2 Bit 1 PRI3[3: Bit 3 Bit 2 Bit 1 PRI5[3: Bit 3 Bit 2 Bit 1 PRI9[3: DS3105 Bit 0 0 Bit 0 0 Bit 0 0 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 BUCKET[1: DIVN1 and DIVN2. When DIVN=1 and LOCK8K ICR register, the 58 of 110 Bit 2 Bit 1 Bit 0 FREQ[3:0] see below 7.4.2.2 and 7.4.2.3 MCR3 register) DS3105 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 IC6 IC5 IC4 registers. See sections 7.6.2. Bit 5 Bit 4 Bit 110 DS3105 Bit 2 Bit 1 Bit 0 IC3 -- -- Bit 2 Bit 1 Bit IC9 VALCR1 but for the IC9 input ...
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... Locked 101 = Pre-locked 2 110 = Pre-locked 111 = Loss-of-lock Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 FREN LOCKPIN -- 110 DS3105 Bit 2 Bit 1 Bit 0 T0STATE[2: ...
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... Automatic source selection (normal operation) Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit VALSR and MSR register bits. However, when the reference 110 DS3105 Bit 2 Bit 1 Bit 0 T0FORCE[3: ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 XOEDGE FRUNHO EFSEN ISR registers. PTAB1 register). See section 7.6. 110 DS3105 Bit 2 Bit 1 Bit 0 SONSDH -- REVERT see below 1 0 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 RSV2 RSV1 -- 110 DS3105 Bit 2 Bit 1 Bit 0 T4FORCE[3: Bit 2 Bit 1 Bit 0 -- IC6SF -- ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 DIG1SS -- -- see below 1 1 MCR7 64 of 110 DS3105 Bit 2 Bit 1 Bit MCR7 register. When register. When RST=0 the default value ...
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... Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 DIG1F[1: DIG2AF=1 DIG2SS = 1 DIG2SS = 19.44 MHz 00 = 6.312 MHz 01 = 38.88 MHz 01 = undefined 10 = undefined MHz 11 = undefined 11 = undefined Bit 5 Bit 4 Bit 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit 0 -- OC6SF[1: ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit LIMINT T0LBW register (T0LBW register) or acquisition bandwidth 66 of 110 DS3105 Bit 2 Bit 1 Bit (T0ABW DLIMIT1 and DLIMIT2. FREQ2 and FREQ3 ...
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... MCLKFREQ is an unsigned integer that adjusts the frequency of the internal Bit 5 Bit 4 Bit 3 MLCKFREQ[15: Bit 5 Bit 4 Bit register, this bit is ignored. See section 7.7.1. 110 Bit 2 Bit Bit 2 Bit MCLK1 register description. Bit 2 Bit DS3105 Bit 0 1 Bit 0 1 Bit 0 0 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 HARDLIM[7: Bit 5 Bit 4 Bit DLIMIT1 68 of 110 DS3105 Bit 2 Bit 1 Bit DLIMIT3 register, if the DPLL Bit 2 Bit 1 Bit 0 -- HARDLIM[9: register description. ...
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... Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 IC6 IC5 IC4 MSR1 register. Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 110 DS3105 Bit 2 Bit 1 Bit 0 IC3 -- -- Bit 2 Bit 1 Bit IC9 Bit 2 Bit 1 Bit ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 DIVN[7: Bit 5 Bit 4 Bit 3 DIVN[15: DIVN1 register description 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit ...
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... Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 UFSW EXTSW PBOFRZ 0 see below 0 MSR2 register. This gives the system a very fast Bit 5 Bit 4 Bit 3 -- T4T0 -- 110 DS3105 Bit 2 Bit 1 Bit 0 PBOEN -- -- Bit 2 Bit 1 Bit PHASE1 and ...
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... The T4 DPLL hard frequency limit is fixed at ±80ppm. and DLIMIT2 Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 AOF6 -- -- 110 DS3105 Bit 2 Bit 1 Bit OPSTATE register. When the T4 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit 0 AOF3 ...
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... LB0L[7: ISR register. Registers LB0U, LB0L, Bit 5 Bit 4 Bit 3 LB0S[7: Bit 5 Bit 4 Bit 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit LB0S and LB0D together specify leaky Bit 2 Bit 1 Bit LB0S ...
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... LB0D register description. and LB1D together configure leaky bucket algorithm 1. and LB2D together configure leaky bucket algorithm 2. and LB3D together configure leaky bucket algorithm 110 DS3105 Bit 2 Bit 1 Bit register description. Bit 2 Bit 1 Bit register description. ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit T0CR1 MCR7 register. See section 7.8.2.3. The default frequency is set by the 7-8) 7- 110 DS3105 Bit 2 Bit 1 Bit 0 OFREQ3[3:0] see below and T4CR1 registers. The Digital1 and ...
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... Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 0 MCR7 register. See section 7.8.2.3. The default frequency is 7-17. The decode of this field is controlled by the value of the OCR5.AOF6 bit. 7- 110 Bit 2 Bit T0CR1 and T4CR1 registers. The DS3105 Bit ...
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... MHz (64 x DS1) 274.944 MHz (8 x E3) 178.944 MHz (4 x DS3) 100.992 MHz (16 x 6312 kHz) 250.000 MHz (GbE ÷ 4) 122.880 MHz (12 x 10.24) 160.000 MHz ( MHz) 104.000 MHz ( MHz) {unused values 110 DS3105 Bit 2 Bit 1 Bit ...
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... MHz (4 x 77.76 MHz) 311.04 MHz (4 x 77.76 MHz) 98.304 MHz (48 x E1) 131.072 MHz (64 x E1) 148.224 MHz (96 x DS1) 98.816 MHz (64 x DS1) 100.992 MHz (16 x 6312 kHz) 250.000 MHz (GbE ÷ 110 DS3105 Bit 2 Bit 1 Bit 0 T0FREQ[2:0] see below The default frequency is controlled by ...
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... Bit Bit 5 Bit 4 Bit 3 0 RSV1 RSV2 MCR9 register, the T0LBW bandwidth is used for acquisition T0ABW bandwidth is used for acquisition while T0LBW bandwidth 110 DS3105 Bit 2 Bit 1 Bit 0 0 T4BW[1: Bit 2 Bit 1 Bit 0 T0LBW[2: ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 0 RSV1 RSV2 MCR9 register, the T0LBW bandwidth is used for is used for T0ABW bandwidth is used for acquisition while T0LBW 80 of 110 DS3105 Bit 2 Bit 1 Bit 0 T0LBW[2: ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 PD2G8K[2: (T4BW 35 Hz ≥ 1.2 1.2 2.5 2 110 DS3105 Bit 2 Bit 1 Bit 0 DAMP[2: register). The default value corresponds ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 PD2G8K[2: 2.5 1.2 1.2 5 2.5 2 110 Bit 2 Bit 1 -- DAMP[2: (T0ABW and T0LBW). The default value 70 Hz 1.2 2 DS3105 Bit 0 1 ...
Page 83
... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 110 DS3105 Bit 2 Bit 1 Bit 0 PD2G[2: T4CR2 register Bit 2 Bit 1 Bit 0 PD2G[2: ...
Page 84
... Bit 0: GPIO1 Output Value (GPIO1O). When GPIO1 is configured as an output (GPIO1D=1) then this bit specifies the output value Low 1 = High Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 GPIO2D GPIO1D GPIO4O 110 DS3105 Bit 2 Bit 1 Bit 0 GPIO3O GPIO2O GPIO1O ...
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... Bit 5 Bit 4 Bit 3 OFFSET[7: MCR10 register) and when the DPLL is not locked. See section 7.7.8. Bit 5 Bit 4 Bit 3 OFFSET[15: OFFSET1 register description 110 DS3105 Bit 2 Bit 1 Bit 0 GPIO3 GPIO2 GPIO1 Bit 2 Bit 1 Bit OFFSET2 Bit 2 Bit 1 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 PBOFF[5: Bit 5 Bit 4 Bit 7.5.3 and 7.7. 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit 0 FINELIM[2: PHLIM2 fields). This field ...
Page 87
... UI 1001 = ±1023 UI 1010 = ±2047 UI 1011 = ±4095 UI 1100 to 1111 = ±8191 UI Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 USEMCPD -- 110 DS3105 Bit 2 Bit 1 Bit 0 COARSELIM[3: 7.7.5 and 7.7.6. ...
Page 88
... Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 PHASE[7: Bit 5 Bit 4 Bit 3 PHASE[15: PHASE1 register description 110 DS3105 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit MCR11 register, PHASE indicates Bit 2 Bit 1 Bit ...
Page 89
... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 PHLKTO[5: Bit 5 Bit 4 Bit 3 SYNCSRC[2:0] 8KINV 110 DS3105 Bit 2 Bit 1 Bit ISR registers). The timeout period in Bit 2 Bit 1 Bit 0 8KPUL 2KINV 2KPUL ...
Page 90
... UI of the sampling clock. See section 7.9. Coincident 01 = 0.5 UI early late 11 = 0.5 UI late Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 PHASE3[1:0] PHASE2[1: 110 DS3105 Bit 2 Bit 1 Bit 0 PHASE1[1: ...
Page 91
... SYNC1, SYNC2 and SYNC3 enabled Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit 3 MONLIM[2: 110 DS3105 Bit 2 Bit 1 Bit 0 SOURCE[3: OFFSET registers, OPSTATE register. See section 7.9.6. ...
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... Protected mode Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. Bit 5 Bit 4 Bit LOS Bit 5 Bit 4 Bit 3 PROT[7: 110 DS3105 Bit 2 Bit 1 Bit 0 GPO OD POL Bit 2 Bit 1 Bit ...
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... JTAG TEST ACCESS PORT AND BOUNDARY SCAN 9.1 JTAG Description The DS3105 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary ...
Page 94
... JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice 110 DS3105 ...
Page 95
... JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update- IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Table 9-1 shows the instructions supported by the DS3105 and their respective operational binary codes. Table 9-1. JTAG Instruction Codes INSTRUCTIONS ...
Page 96
... Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device identification code for the DS3105 is shown in Table 9-2. Table 9-2. JTAG ID Code DEVICE ...
Page 97
... CONDITIONS VDD VDDIO -40°C to +85°C) A SYMBOL CONDITIONS I Note Note 1, 2 DDIO I Note 3 DDOC6 OUT Figure 10- 110 DS3105 MIN TYP MAX UNITS 1.62 1.8 1.98 V 3.135 3.3 3.465 V -40 +85 °C -40 +125 °C MIN TYP MAX UNITS TBD TBD mA TBD ...
Page 98
... OHLVDS V Note 1 OLLVDS V ODLVDS V 25°C, Note 1 OSLVDS V DOSLVDS for details. = -40°C to +85°C) A SYMBOL CONDITIONS V ODPECL V 25°C, Note 1 OSPECL V DOSPECL for details 110 DS3105 MIN TYP MAX UNITS 2.0 5.5 V -0.3 +0.8 V μA -10 +10 μA -85 +10 μA -10 +85 μA -10 +10 2.4 VDDIO V 2 ...
Page 99
... Preliminary. Subject to Change Without Notice. ICnPOS OCnPOS DS3105 (5%) iICnNEG OCnNEG 3.3V 130Ω 130Ω 50 Ω ICnPOS 50 Ω ICnNEG 82Ω 82Ω GND 3.3V 82Ω 50 Ω OCnPOS . Ω OCnNEG 130Ω GND 99 of 110 DS3105 50 Ω LVDS 100Ω 50 Ω (5%) RCVR DS3105 82Ω PECL RCVR 130Ω ...
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... DS3105 TYP MAX 500μs (2kHz) 500μs (2kHz) ...
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... MIN TYP MAX f 6 BUS t 100 CYC t 15 SUC t 15 HDC t 50 CLKH t 50 CLKL t 5 SUI t 15 HDI DIS HDO t HDC DIS t HDO t HDC DIS DS3105 UNITS MHz ...
Page 102
... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. = -40°C to +85°C) (Figure 10-5) A SYMBOL MIN t1 t2/ 100 102 of 110 DS3105 TYP MAX UNITS 1000 ns 500 ...
Page 103
... Figure 10-6. Reset Pin Timing Diagram t1 RST SONSDH X valid OxF[2:0] SRCSW Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. = -40°C to +85°C) (Figure 10-6) A SYMBOL X 103 of 110 MIN TYP MAX UNITS t1 1000 DS3105 ...
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... Figure 11-1 PIN NAME PIN NUMBER MFSYNC 18 38 O3F2 / LOCK OC3 56 OC6NEG 19 OC6POS 20 REFCLK 6 RST 48 SCLK 47 SDI 43 SDO 52 64 SRCSW 13 SYNC1 28 SYNC2 33 35 TEST 2 VDD 27, 39, 57, 58 VDDIO 14, 32, 54, 61 VDD_OC6 22 1, 15, 16, 31, 40, 53, VSS 60, 62 VSS_OC6 21 DS3105 show pin ...
Page 105
... AVDD_PLL3 9 AVSS_PLL3 10 AVDD_PLL4 11 AVSS_PLL4 12 SRCSW 13 VDDIO 14 VSS 15 VSS 16 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. DS3105 105 of 110 DS3105 RST 48 47 SCLK 46 O6F1/GPIO2 O6F0/GPIO1 SDI 42 CPHA 41 JTMS 40 VSS 39 VDD ...
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... MECHANICAL INFORMATION Figure 12-1. LQFP Mechanical Dimensions Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. 106 of 110 DS3105 ...
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... Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. MIN -40°C -40°C ) vs. Airflow JA THETA-JA (θ TBD °C/W TBD °C/W TBD °C/W 107 of 110 DS3105 TYP MAX — +85°C — +125°C TBD °C/W TBD °C/W TBD °C/W ...
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... Motorola is a registered trademark of Motorola, Inc. Semtech and Semtech Corp. are registered trademarks of Semtech Corporation. SPI is a trademark of Motorola, Inc. Telcordia is a registered trademark of Telcordia Technologies Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. 108 of 110 DS3105 ...
Page 109
... T4LOCK to 0. and the DLIMIT1 and DLIMIT3:FLLOL descriptions to indicate that the T4 Table 7-14 from “Possible Frequencies” to “Standard Frequencies”. 5 feature bullet and section max to 50ns. DV 109 of 110 DS3105 Table 5 bullets, and added Table 6-3, the name of INTCR bit 3 7.8.2.6 text to indicate spec for OC1B ...
Page 110
... In sections 7.11 and 7.13, added notes to indicate that system software must wait at least 100µs after reset is deasserted before initializing the device Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. Preliminary. Subject to Change Without Notice. DESCRIPTION 110 of 110 DS3105 ...