C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 208

MCU, MPU & DSP Development Tools With C8051F124 MCU

C8051F124TB

Manufacturer Part Number
C8051F124TB
Description
MCU, MPU & DSP Development Tools With C8051F124 MCU
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F124TB

Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
208
Bits 7–6: Unused.
Bits 5–4: FLRT: Flash Read Time.
Bits 3–1: RESERVED. Read = 000b. Must Write 000b.
Bit 0:
Important Note: When changing the FLRT bits to a lower setting (e.g. when changing from a
R/W
Bit7
-
These bits should be programmed to the smallest allowed value, according to the system
clock speed.
00: SYSCLK < 25 MHz.
01: SYSCLK < 50 MHz.
10: SYSCLK < 75 MHz.
11: SYSCLK < 100 MHz.
FLWE: Flash Write/Erase Enable.
This bit must be set to allow Flash writes/erasures from user software.
0: Flash writes/erases disabled.
1: Flash writes/erases enabled.
value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be
disabled using the CCH0CN register (see SFR Definition 16.1).
R/W
Bit6
-
SFR Definition 15.2. FLSCL: Flash Memory Control
R/W
Bit5
FLRT
R/W
Bit4
Reserved Reserved Reserved
Rev. 1.4
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
FLWE
R/W
Bit0
0xB7
0
SFR Address:
10000000
Reset Value

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