C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 245

• Manufacturer Part Number: C8051F124TB
• Description: MCU, MPU & DSP Development Tools With C8051F124 MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F124TB

• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit7:
Bit6:
Bits5–3: PCA0ME: PCA0 Module I/O Enable Bits.
Bit2:
Bit1:
Bit0:
CP0E
R/W
Bit7
CP0E: Comparator 0 Output Enable Bit.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
ECI0E: PCA0 External Counter Input Enable Bit.
0: PCA0 External Counter Input unavailable at Port pin.
1: PCA0 External Counter Input (ECI0) routed to Port pin.
000: All PCA0 I/O unavailable at port pins.
001: CEX0 routed to port pin.
010: CEX0, CEX1 routed to 2 port pins.
011: CEX0, CEX1, and CEX2 routed to 3 port pins.
100: CEX0, CEX1, CEX2, and CEX3 routed to 4 port pins.
101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 routed to 6 port pins.
UART0EN: UART0 I/O Enable Bit.
0: UART0 I/O unavailable at Port pins.
1: UART0 TX routed to P0.0, and RX routed to P0.1.
SPI0EN: SPI0 Bus I/O Enable Bit.
0: SPI0 I/O unavailable at Port pins.
1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins. Note that the NSS signal is not
assigned to a port pin if the SPI is in 3-wire mode. See Section “
Interface and On-Chip XRAM
SMB0EN: SMBus0 Bus I/O Enable Bit.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 SDA and SCL routed to 2 Port pins.
ECI0E
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0
R/W
Bit6
R/W
Bit5
PCA0ME
R/W
Bit4
” on page
Rev. 1.4
R/W
Bit3
219
C8051F120/1/2/3/4/5/6/7
for more information.
UART0EN SPI0EN
R/W
Bit2
C8051F130/1/2/3
R/W
Bit1
17. External Data Memory
SFR Address:
SMB0EN 00000000
SFR Page:
R/W
Bit0
0xE1
F
Reset Value
245