C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 267

MCU, MPU & DSP Development Tools With C8051F124 MCU

C8051F124TB

Manufacturer Part Number
C8051F124TB
Description
MCU, MPU & DSP Development Tools With C8051F124 MCU
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F124TB

Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19.4.2. Clock Rate Register
Bits7–0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset
R/W
Bit7
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master
mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The
timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation , where SMB0CR is the
unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in
MHz:
The resulting SCL signal high and low times are given by the following equations, where
SYSCLK is the system clock frequency in Hz:
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the
following equation:
R/W
Bit6
SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate
SMB0CR
T
HIGH
R/W
Bit5
T
LOW
T
BFT
4
=
288 0.85
10
R/W
Bit4
4
258 SMB0CR
256 SMB0CR
4
------------------------------------------------------------- -
Rev. 1.4
256 SMB0CR
R/W
Bit3
SYSCLK
--------------------- -
SYSCLK
C8051F120/1/2/3/4/5/6/7
4
SYSCLK
R/W
Bit2
 1.125
SYSCLK
+
C8051F130/1/2/3
+
1
625ns
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xCF
0
00000000
Reset Value
267

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