5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 68

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5M80ZT100C5N

Manufacturer Part Number
5M80ZT100C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M80ZT100C5N

Cpld Type
FLASH
No. Of Macrocells
64
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
80
Number Of Macrocells
64
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
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Part Number:
5M80ZT100C5N
Manufacturer:
ALTERA
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825
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Manufacturer:
Altera
Quantity:
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Manufacturer:
ALTERA
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Training
Online Training
66
Course Category
Getting started
Design languages
Software overview
and design entry
Verification
and debugging
Altera Product Catalog
Altera Free Online Training Courses (Courses Are Approximately One Hour in Length)
Course Titles
Read Me First!
Basics of Programmable Logic
How to Begin a Simple FPGA Design
VHDL Basics
Verilog HDL Basics
SystemVerilog with the Quartus II Software
Best HDL Design Practices for Timing Closure
Using Quartus II Software: An Introduction
The Quartus II Software Interactive Tutorial
The Quartus II Software Design Series: Foundation
(note: this training is equivalent to the instructor-led course of the same name)
What’s New in the Quartus II Software Version 11.0
Setting Up Floating Licenses
Synplify Pro Tips and Tricks
Using Quartus II Software: Schematic Design
Quartus II Settings and Assignments
Introduction to Incremental Compilation
Team-Based Design Flows Using Quartus II Incremental Compilation
I/O System Design
Advanced I/O System Design
Managing Metastability with the Quartus II Software
Overview of Mentor Graphics ModelSim Software
Simulating Designs with 3rd Party EDA Simulators
SignTap II Embedded Logic Analyzer
Using Quartus II Software: Chip Planner
Debugging and Communicating with an FPGA Using the Virtual JTAG Megafunction
System Console Overview
Debugging JTAG Chain Integrity
2011
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