5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 78

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ordering Codes
Reference
76
Transceiver Speed Grade
For Stratix V GX/GS FPGAs only
1: 14.1 Gbps
2: 12.5 Gbps
3: 8.5 Gbps
For Stratix V GT FPGAs only
2: 28G
3: 25G
4: 20G
5SE:
5SGS: Stratix V GS
5SGT: Stratix V GT
5SGX: Stratix V GX
5AGX: Arria V GX
5AGT: Arria V GT
5SE
5SGS: M, E
5SGT: M, C
5SGX: M, E, C
5AGX: B, M, F
5AGT: B, M, F
5SE:
5SGS: D2, D3, D4, D5, D6, D8
5SGT: C5, C7
5SGX: A3, A4, A5, A7, A9, AB, B5, B6
5AGX: A1, A3, A5, A7, B1, B3, B5, B7
5AGT: D3, D5
D: 9
E: 12
F: 16
G: 18
H: 24
K: 36
N: 48
R: 66
Transceiver Channels
Altera Product Catalog
Hardened IP Blocks
Family Signature
Device Type
Stratix V E
E9, EB
5SGX
E
•
2011
•
For Arria V GX FPGAs only
4: 6.375 Gbps
5: 5G
6: 3.125 Gbps
For Arria V GT FPGAs only
3: 10.3125 Gbps
A7
www.altera.com
N
3
F
45
C
F: FineLine BGA
H: Hybrid FineLine BGA
Package Type
3
X
Stratix V GT
Stratix V GX
Stratix V GS
Stratix V E
Arria V GX
Arria V GT
Devices
N
Pin count code
C: Commercial (0˚C to 85˚C)
I: Industrial (-40˚C to 100˚C)
Operating Temperature
ES: Engineering sample
N: RoHS compliant
Optional Character
23
27
29
31
35
40
43
45
RoHS Compliant
Optional Suffix
Fast
1
Core Speed
ES
Pin Count
2
TBD
3
4 5 6
Pin count
1,152
1,517
1,760
1,932
Slow
484
672
780
896