WM8523GEFL/RV Wolfson Microelectronics, WM8523GEFL/RV Datasheet - Page 15
![IC, DAC, STEREO, 2VRMS, 2CH, 24QFN](/photos/19/1/190137/ge24qfn007-40_sml.jpg)
WM8523GEFL/RV
Manufacturer Part Number
WM8523GEFL/RV
Description
IC, DAC, STEREO, 2VRMS, 2CH, 24QFN
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8523GEFLRV.pdf
(50 pages)
Specifications of WM8523GEFL/RV
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Digital Ic Case Style
QFN
No. Of Pins
24
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Package
RoHS Compliant
Data Interface
I2C, Serial, SPI
Supply Voltage Range - Analogue
2.97V To 3.63V
Rohs Compliant
Yes
Pre-Production
POWER ON RESET CIRCUIT
w
Figure 6 Internal Power on Reset Circuit Schematic
The WM8523 includes an internal Power-On-Reset circuit, as shown in Figure 6, which is used to reset
the DAC digital logic into a default state after power up. The POR circuit is powered by AVDD and has
as its inputs VMID and LINEVDD. It asserts POR low if VMID or LINEVDD are below a minimum
threshold.
Figure 7 Typical Power Timing Requirements
Figure 7 shows a typical power-up sequence where LINEVDD comes up with AVDD. When AVDD goes
above the minimum threshold, V
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. After
VMID rises to V
state and writes to the control interface may take place.
On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum threshold
V
pora_low
.
pord_hi
and AVDD rises to V
pora
, there is enough voltage for the circuit to guarantee POR is asserted
pora_hi,
POR is released high and all registers are in their default
PP, Rev 3.0, July 2009
WM8523
15