WM8523GEFL/RV Wolfson Microelectronics, WM8523GEFL/RV Datasheet - Page 23
![IC, DAC, STEREO, 2VRMS, 2CH, 24QFN](/photos/19/1/190137/ge24qfn007-40_sml.jpg)
WM8523GEFL/RV
Manufacturer Part Number
WM8523GEFL/RV
Description
IC, DAC, STEREO, 2VRMS, 2CH, 24QFN
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8523GEFLRV.pdf
(50 pages)
Specifications of WM8523GEFL/RV
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Digital Ic Case Style
QFN
No. Of Pins
24
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Package
RoHS Compliant
Data Interface
I2C, Serial, SPI
Supply Voltage Range - Analogue
2.97V To 3.63V
Rohs Compliant
Yes
Pre-Production
w
In DSP mode, the left channel MSB is available on either the 1
BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK.
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 19 and Figure
20. In device slave mode, Figure 21 and Figure 22, it is possible to use any length of frame pulse less
than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the
rising edge of the next frame pulse.
Figure 19 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 20 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
Figure 21 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
st
(mode B) or 2
PP, Rev 3.0, July 2009
nd
(mode A) rising edge of
Right channel data
WM8523
23