25LC020A-H/SN Microchip Technology, 25LC020A-H/SN Datasheet - Page 8

• Manufacturer Part Number: 25LC020A-H/SN
• Description: 2K, 256 X 8, 2.5V SER EE 150C 8 SOIC 3.90mm (.150") TUBE
• Manufacturer: Microchip Technology

Specifications of 25LC020A-H/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25LCXXXA
3.0
3.1
The 25LCXXXA are low-density serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete I/
O lines programmed properly in firmware to match the
SPI protocol.
The 25LCXXXA contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXXA in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 3-1:
DS22136B-page 8
Instruction Name
Note:
WRITE
READ
WRDI
WREN
RDSR
WRSR
FUNCTIONAL DESCRIPTION
Principles of Operation
x = don’t care.
For the 24LC040A device, A
For the 24LC020A and 24LC010A devcies, A
INSTRUCTION SET
Instruction Format
0000 A
0000 A
0000 x100
0000 x110
0000 x101
0000 x001
8
8
011
010
8
is the 9
®
micro-
th
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read STATUS register
Write STATUS register
Preliminary
address bit, which is used to address the entire 512 byte array.
8
is a don’t care.
BLOCK DIAGRAM
HOLD
SCK
WP
SO
CS
SI
I/O Control
Register
STATUS
Logic
Description
V
V
CC
SS
Memory
Control
© 2009 Microchip Technology Inc.
Logic
Dec
X
Sense Amp.
R/W Control
Y Decoder
HV Generator
Page Latches
EEPROM
Array