AD7265BSUZ Analog Devices Inc, AD7265BSUZ Datasheet - Page 7

• Manufacturer Part Number: AD7265BSUZ
• Description: IC,Data Acquisition System,3-CHANNEL,12-BIT,TQFP,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7265BSUZ

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Number Of Elements: 2
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 1MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 21mW
• Differential Linearity Error: -0.99LSB/1.5LSB
• Integral Nonlinearity Error: ±1.5LSB
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / Rohs Status: Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1, 29
2
3
4, 20
5, 6, 19
7 to 12
13 to 18
21
22
23 to 25
26
27
REF SELECT
Mnemonic
DGND
REF SELECT
AV
D
AGND
V to V
V
RANGE
SGL/DIFF
A2 to A0
CS
SCLK
A1
B6
CAP
DD
D
DGND
AGND
AGND
to V
AV
CAP
A, D
V
V
DD
A1
A2
A
B1
A6
CAP
1
2
3
4
5
6
7
8
Figure 2. 32-Lead CP-32-2
B
(Not to Scale)
Description
Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used
as the reference source for both ADC A and ADC B. In addition, Pin D
decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the
AD7265 through the D
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The
AV and DV
transient basis. This supply should be decoupled to AGND.
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference
can be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect
to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential
analog input channel pairs. See Table 6.
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog
input channels. If this pin is tied to a logic low, the analog input range is 0 V to V
high when CS goes low, the analog input range is 2 × V . See the Analog Input Selection section for details.
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A
logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265
and framing the serial data transfer.
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This
clock is also used as the clock source for the conversion process.
PIN 1
INDICATOR
AD7265
TOP VIEW
DD
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
24
23
22
21
20
19
18
17
A1
A2
SGL/DIFF
RANGE
D
AGND
V
V
B1
B2
CAP
B
CAP
A pin and/or the D
Rev. A | Page 7 of 28
CAP
B pin.
REF
REF SELECT
D
DGND
AGND
AGND
AV
CAP
V
V
DD
A1
A2
A
1
2
3
4
5
6
7
8
CAP
Figure 3. 32-Lead SU-32-2
32 31 30 29 28 27 26 25
9
A and Pin D
10 11 12 13 14 15 16
PIN 1
(Not to Scale)
TOP VIEW
AD7265
REF
. If this pin is tied to a logic
CAP
B must be tied to
24
23
22
21
20
19
18
17
A1
A2
SGL/DIFF
RANGE
D
AGND
V
V
B1
B2
CAP
B
AD7265