AD7477ARTZ-REEL7 Analog Devices Inc, AD7477ARTZ-REEL7 Datasheet - Page 18

• Manufacturer Part Number: AD7477ARTZ-REEL7
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,TSOP,6PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7477ARTZ-REEL7

• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7477CBZ - BOARD EVALUATION FOR AD7477
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

time is another cycle, i.e., 1 µs, the AD7476A/AD7477A/
AD7478A can be said to dissipate 17.5 mW for 2 µs during each
conversion cycle. If the throughput rate is 100 kSPS, the cycle time is
10 µs and the average power dissipated during each cycle is
(2/10)
and the devices are again in power-down mode between conver-
sions, then the power dissipation during normal operation is
5.1 mW. The AD7476A/AD7477A/AD7478A can now be said
to dissipate 5.1 mW for 2 µs during each conversion cycle. With
a throughput rate of 100 kSPS, the average power dissipated
during each cycle is (2/10)
shows the power versus the throughput rate when using the
power-down mode between conversions with both 5 V and 3 V
supplies.
The power-down mode is intended for use with throughput
rates of approximately 333 kSPS and under, since at higher
sampling rates there is no power saving made by using the
power-down mode.
AD7476A/AD7477A/AD7478A
0.01
100
SDATA
SDATA
THREE-STATE
0.1
10
SCLK
(17.5 mW) = 3.5 mW. If V
1
SCLK
CS
0
CS
Figure 12. Power vs. Throughput
THREE-
STATE
50
V
t
V
2
t
DD
DD
Z
2
100
Z
1
= 3V, SCLK = 20MHz
= 5V, SCLK = 20MHz
t
3
1
t
THROUGHPUT – kSPS
ZERO
3
ZERO
4 LEADING ZEROS
(5.1 mW) = 1.02 mW. Figure 12
150
4 LEADING ZEROS
2
2
ZERO
ZERO
DD
200
Figure 13. AD7476A Serial Interface Timing Diagram
Figure 14. AD7477A Serial Interface Timing Diagram
= 3 V, SCLK = 20 MHz,
3
3
ZERO
t
4
ZERO
250
4
4
DB11
t
CONVERT
300
DB9
t
t
6
4
t
6
t
5
CONVERT
5
t
350
DB10
7
DB8
t
7
–18–
1/THROUGHPUT
1/ THROUGHPUT
SERIAL INTERFACE
Figures 13, 14, and 15 show the detailed timing diagrams for
serial interfacing to the AD7476A, AD7477A, and AD7478A,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information from the AD7476A/
AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode and
takes the bus out of three-state; the analog input is sampled at this
point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion will require 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-and-
hold will go back into track on the next SCLK rising edge, as shown
in Figure 13 at Point B. On the 16th SCLK falling edge, the SDATA
line will go back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge, as shown in
Figure 13. Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476A.
For the AD7477A, the conversion will require 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold will go back into track on the next rising edge as
shown in Figure 14 at Point B. If the rising edge of CS occurs
before 14 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state. If 16 SCLKs
are considered in the cycle, SDATA will return to three-state on
the 16th SCLK falling edge, as shown in Figure 14.
For the AD7478A, the conversion will require 12 SCLK cycles
to complete. The track-and-hold will go back into track on the
rising edge after the 11th falling edge, as shown in Figure 15 at
Point B. If the rising edge of CS occurs before 12 SCLKs have
13
13
B
DB2
DB0
B
14
t
5
14
t
5
DB1
2 TRAILING ZEROS
ZERO
15
15
DB0
ZERO
t
8
t
16
8
16
THREE-STATE
THREE-STATE
t
QUIET
t
QUIET
t
1
t
1
REV. C