AD7477ARTZ-REEL7 Analog Devices Inc, AD7477ARTZ-REEL7 Datasheet - Page 19

• Manufacturer Part Number: AD7477ARTZ-REEL7
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,TSOP,6PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7477ARTZ-REEL7

• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7477CBZ - BOARD EVALUATION FOR AD7477
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

elapsed, the conversion will be terminated and the SDATA line
will go back into three-state. If 16 SCLKs are considered in the
cycle, SDATA will return to three-state on the 16th SCLK
falling edge, as shown in Figure 15.
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the sec-
ond leading zero. Thus, the first falling clock edge on the serial
clock has the first leading zero provided and also clocks out the
second leading zero. For the AD7476A, the final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK will clock out the second leading zero, which can be read
in the first rising edge. However, the first leading zero that was
clocked out when CS went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK will
clock out the last bit and it could be read in the 15th rising
SCLK edge.
If CS goes low just after one SCLK falling edge has elapsed, CS
will clock out the first leading zero as it did before, and it may
be read in the SCLK rising edge. The next SCLK falling edge
will clock out the second leading zero, and it may be read in the
following rising edge.
AD7478A in a 12 SCLK Cycle Serial Interface
For the AD7478A, if CS is brought high in the 12th rising edge
after the four leading zeros and the eight bits of the conversion
have been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a f
REV. C
SDATA
SCLK
THREE-STATE
CS
SDATA
THREE-STATE
SCLK
CS
t
2
Z
1
t
3
ZERO
4 LEADING ZEROS
t
2
Z
2
1
ZERO
ZERO
Figure 16. AD7478A in a 12 SCLK Cycle Serial Interface
Figure 15. AD7478A Serial Interface Timing Diagram
4 LEADING ZEROS
SCLK
t
CONVERT
3
2
ZERO
ZERO
= 20 MHz and a
t
6
4
3
DB7
ZERO
t
4
10.5(1/
t
CONVERT
11
4
f
B
SCLK
1/THROUGHPUT
DB7
t
7
)
12
5
–19–
ZERO
1/ THROUGHPUT
DB6
throughput of 1.2 MSPS give a cycle time of t
t
This 298 ns satisfies the requirement of 225 ns for t
Figure 16, t
t
the minimum requirement of 50 ns.
MICROPROCESSOR INTERFACING
The serial interface on the AD7476A/AD7477A/AD7478A
allows the part to be directly connected to a range of different
microprocessors. This section explains how to interface the
AD7476A/AD7477A/AD7478A with some of the more common
microcontroller and DSP serial interface protocols.
AD7476A/AD7477A/AD7478A to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize the
data transfer operations with peripheral devices, such as the
AD7476A/AD7477A/AD7478A. The CS input allows easy inter-
facing between the TMS320C541 and the AD7476A/AD7477A/
AD7478A without any glue logic required. The serial port of the
TMS320C541 is set up to operate in burst mode (FSM = 1 in
the serial port control register, SPC) with internal serial clock
CLKX (MCM = 1 in the SPC register) and internal frame signal
(TXM = 1 in the SPC register), so both pins are configured as
outputs. For the AD7476A, the word length should be set to 16 bits
(FO = 0 in the SPC register). This DSP only allows frames with
a word length of 16 bits or 8 bits. Therefore, in the case of the
AD7477A and AD7478A where 14 bits and 12 bits were required,
the FO bit would be set up to 16 bits. This means to obtain the
conversion result, 16 SCLKs are needed. In both situations, the
remaining SCLKs will clock out trailing zeros. For the AD7477A,
two trailing zeros will be clocked out in the last two clock cycles;
for the AD7478A, four trailing zeros will be clocked out.
ACQ
8
13
= 36 ns max. This allows a value of 237 ns for t
4 TRAILING ZEROS
ZERO
= 833 ns. With t
14
t
11
5
ZERO
ACQ
B
DB0
t
AD7476A/AD7477A/AD7478A
8
is comprised of 0.5 (1/f
15
12
t
ZERO
8
2
= 10 ns min, this leaves t
THREE-STATE
16
t
ACQ
t
QUIET
THREE-STATE
t
1
t
QUIET
SCLK
t
) + t
1
2
+10.5 (1/f
ACQ
8
+ t
QUIET
to be 298 ns.
QUIET
ACQ
, satisfying
SCLK
. From
, where
) +