AD9272BSVZRL-65 Analog Devices Inc, AD9272BSVZRL-65 Datasheet - Page 29

• Manufacturer Part Number: AD9272BSVZRL-65
• Description: 12Bit 65 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-65

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Variable Gain Amplifier
The differential X-AMP VGA provides precise input attenuation
and interpolation. It has a low input-referred noise of 3.8 nV/√Hz
and excellent gain linearity. A simplified block diagram is shown in
Figure 50.
The input of the VGA is a 14-stage differential resistor ladder with
3.5 dB per tap. The resulting total gain range is 42 dB, which
allows for range loss at the endpoints. The effective input resistance
GAIN±
VIN
VIP
Figure 48. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
Figure 49. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations
g
0.6
0.5
0.4
0.3
0.2
0.1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
m
0
0
0
0
PGA GAIN = 30dB
PGA GAIN = 30dB
PGA GAIN = 27dB
3dB
PGA GAIN = 30dB
GAIN INTERPOLATOR
0.2
0.2
Figure 50. Simplified VGA Schematic
0.4
0.4
PGA GAIN = 21dB
0.6
0.6
PGA GAIN = 24dB
GAIN+ (V)
GAIN+ (V)
0.8
0.8
PGA GAIN = 27dB
PGA GAIN = 21dB
PGA GAIN = 24dB
1.0
1.0
1.2
1.2
+
–
1.4
1.4
POSTAMP
POSTAMP
1.6
1.6
Rev. C | Page 29 of 44
per side is 180 Ω nominally for a total differential resistance of
360 Ω. The ladder is driven by a fully differential input signal from
the LNA. LNA outputs are dc-coupled to avoid external decoupling
capacitors. The common-mode voltage of the attenuator and the
VGA is controlled by an amplifier that uses the same midsupply
voltage derived in the LNA, permitting dc coupling of the LNA
to the VGA without introducing large offsets due to common-
mode differences. However, any offset from the LNA becomes
amplified as the gain increases, producing an exponentially
increasing VGA output offset.
The input stages of the X-AMP are distributed along the ladder,
and a biasing interpolator, controlled by the gain interface, deter-
mines the input tap point. With overlapping bias currents, signals
from successive taps merge to provide a smooth attenuation range
from −42 dB to 0 dB. This circuit technique results in linear-in-dB
gain law conformance and low distortion levels—only deviating
±0.5 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.
The X-AMP inputs are part of a programmable gain feedback
amplifier that completes the VGA. Its bandwidth is approximately
100 MHz. The input stage is designed to reduce feedthrough to
the output and to ensure excellent frequency response uniformity
across the gain setting.
Gain Control
The gain control interface, GAIN±, is a differential input. V
varies the gain of all VGAs through the interpolator by selecting
the appropriate input stages connected to the input attenuator.
For GAIN− at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is
0 V to 1.6 V, with the best gain linearity from about 0.16 V to
1.44 V, where the error is typically less than ±0.5 dB. For
GAIN+ voltages greater than 1.44 V and less than 0.16 V, the
error increases. The value of GAIN+ can exceed the supply
voltage by 1 V without gain foldover.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
There are two ways in which the GAIN+ and GAIN− pins can
be interfaced. Using a single-ended method, a Kelvin type of
connection to ground can be used as shown in Figure 51. For
driving multiple devices, it is preferable to use a differential
method, as shown in Figure 52. In either method, the GAIN+
and GAIN− pins should be dc-coupled and driven to accom-
modate a 1.6 V full-scale input.
AD9272
GAIN+
GAIN–
Figure 51. Single-Ended GAIN± Pins Configuration
0.01µF
0.01µF
100Ω
CONNECTION
KELVIN
50Ω
0V TO 1.6V DC
AD9272
GAIN