AD9272BSVZRL-65 Analog Devices Inc, AD9272BSVZRL-65 Datasheet - Page 35

• Manufacturer Part Number: AD9272BSVZRL-65
• Description: 12Bit 65 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-65

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12. Flexible Output Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
–200
–400
–600
600
400
200
–200ps
25
20
15
10
0
5
0
–1.5ns
EYE: ALL BITS
–1.0ns
–100ps
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard output
PN sequence long
PN sequence short
One-/zero-word toggle
User input
1-/0-bit toggle
1× sync
One bit high
Mixed bit frequency
–0.5ns
0ps
0ns
0.5ns
ULS: 2396/2396
100ps
1.0ns
Digital Output Word 1
N/A
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
N/A
N/A
1111 1111 1111
Register 0x19 to Register 0x1A
1010 1010 1010
0000 0011 1111
1000 0000 0000
1010 0011 0011
1.5ns
200ps
Rev. C | Page 35 of 44
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
To change the output data format to twos complement, see the
Memory Map section.
Table 11. Digital Output Coding
Code
4095
2048
2047
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 960 Mbps
(12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 17 for details on enabling this
feature.
Two output clocks are provided to assist in capturing data from
the AD9272. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9272 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
(VIN+) − (VIN−),
Input Span = 2 V p-p (V)
+1.00
0.00
−0.000488
−1.00
Digital Output Word 2
N/A
1111 1111 1111
0000 0000 0000
0101 0101 0101
N/A
N/A
Register 0x1B to Register 0x1C
N/A
N/A
N/A
1000 0000 0000
0000 0000 0000
N/A
Digital Output Offset Binary
(D11...D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Subject to Data
Format Select
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
AD9272