AD9516-4BCPZ Analog Devices Inc, AD9516-4BCPZ Datasheet - Page 75
![Clock IC With 1.8GHz On-chip VCO](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9516-4BCPZ
Manufacturer Part Number
AD9516-4BCPZ
Description
Clock IC With 1.8GHz On-chip VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9516-4BCPZ.pdf
(80 pages)
Specifications of AD9516-4BCPZ
Pll
Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:14
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9516-4/PCBZ - BOARD EVAL FOR AD9516-4 1.8GHZ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
PROTEK
Quantity:
15 700
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
ADI
Quantity:
996
Part Number:
AD9516-4BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Reg.
Addr.
(Hex)
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
Bits
5
4
3
2
1
0
0
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
5
4
3
2
1
0
0
Name
Bypass Divider 3.2
Bypass Divider 3.1
Divider 3 nosync
Divider 3 force high
Start High Divider 3.2
Start High Divider 3.1
Divider 3 DCCOFF
Low Cycles Divider 4.1
High Cycles Divider 4.1
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Low Cycles Divider 4.2
High Cycles Divider 4.2
Bypass Divider 4.2
Bypass Divider 4.1
Divider 4 nosync
Divider 4 force high
Start High Divider 4.2
Start High Divider 4.1
Divider 4 DCCOFF
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
0: forces low (default).
1: forces high.
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
0: forces low (default).
1: forces high.
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Description
Force Divider 3 output high. Requires that nosync also be set.
Forces Divider 4 output high. Requires that nosync also be set.
Rev. A | Page 75 of 80
AD9516-4