AD9518-2ABCPZ-RL7 Analog Devices Inc, AD9518-2ABCPZ-RL7 Datasheet - Page 48
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AD9518-2ABCPZ-RL7
Manufacturer Part Number
AD9518-2ABCPZ-RL7
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-2ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-2ABCPZ-RL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.33GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
AD9518-2
Table 44. PLL
Reg.
Addr.
(Hex)
0x010
0x011
0x012
0x013
0x014
0x015
0x016
Bits
7
[6:4]
[3:2]
[1:0]
[7:0]
[5:0]
[5:0]
[7:0]
[4:0]
7
6
5
4
3
PFD polarity
CP mode
14-bit R divider,
6-bit A counter
13-bit B counter,
Name
CP current
PLL power-
down
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
13-bit B counter,
Bits[7:0] (LSB)
Bits[12:8] (MSB)
Set CP pin to V
Reset R counter
Reset A, B counters
Reset all counters
B counter
bypass
CP
/2
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
0
0
0
0
1
1
1
1
Charge pump operating mode.
3
0
0
1
1
PLL operating mode.
1
0
0
1
1
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Sets the CP pin to one-half of the V
0: CP normal operation (default).
1: CP pin set to V
Resets R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Resets A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
5
0
0
1
1
0
0
1
1
2
0
1
0
1
0
0
1
0
1
4
0
1
0
1
0
1
0
1
Charge Pump Mode
High impedance state.
Force source current (pump up).
Force sink current (pump down).
Normal operation (default).
Mode
Normal operation.
Asynchronous power-down (default).
Normal operation.
Synchronous power-down.
I
0.6.
1.2.
1.8.
2.4.
3.0.
3.6.
4.2.
4.8 (default).
CP
CP
/2.
(mA)
Rev. A | Page 48 of 64
CP
supply voltage.