AD9518-2ABCPZ-RL7 Analog Devices Inc, AD9518-2ABCPZ-RL7 Datasheet - Page 50

• Manufacturer Part Number: AD9518-2ABCPZ-RL7
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9518-2ABCPZ-RL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.33GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.33GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-2
Reg.
Addr.
(Hex)
0x017
0x018
0x019
Bits
[1:0]
[6:5]
4
3
[2:1]
[0]
[7:6]
[5:3]
[2:0]
Lock detect
VCO cal
R, A, B counters
Name
Antibacklash
pulse width
counter
Digital lock detect
window
Disable digital
lock detect
divider
VCO cal now
SYNC pin reset
R path delay
N path delay
Description
1
0
0
1
1
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
0
0
1
1
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not
zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit
(Register 0x232, Bit 0).
7
0
0
1
1
R path delay (default = 0x00) (see
N path delay (default = 0x00) (see
0
0
1
0
1
5
0
1
0
1
1
0
1
0
1
6
0
1
0
1
Antibacklash Pulse Width (ns)
2.9 (default).
1.3.
6.0.
2.9.
PFD Cycles to Determine Lock
5 (default).
16.
64.
255.
VCO Calibration Clock Divider
2.
4.
8.
16 (default).
Action
Does nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Does nothing on SYNC .
Rev. A | Page 50 of 64
Table 2
Table 2
).
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