AD9520-2/PCBZ Analog Devices Inc, AD9520-2/PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9520-2/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-2/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.335 GHz; Output = 2.335 GHz
VCO = 2.175 GHz; Output = 2.175 GHz
VCO = 2.05 GHz; Output = 2.05 GHz
VCO = 2.212 GHz; LVPECL = 245.76 MHz; PLL LBW = 66 kHz
VCO = 2.212 GHz; LVPECL = 122.88 MHz; PLL LBW = 66 kHz
VCO = 2.212 GHz; LVPECL = 61.44 MHz; PLL LBW = 66 kHz
VCO = 2.177 GHz; LVPECL = 155.52 MHz; PLL LBW = 2.1 kHz
VCO = 2.212 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.2 kHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Typ
−49
−80
−105
−125
−140
−146
−52
−83
−108
−128
−142
−147
−55
−84
−110
−130
−142
−147
Rev. 0 | Page 11 of 84
Min
Min
Max
Typ
569
599
145
155
169
Typ
321
324
336
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Max
Max
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
Unit
fs rms
fs rms
fs rms
Test Conditions/Comments
Internal VCO; direct-to-LVPECL output and for
loop bandwidths < 1 kHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 19.44 MHz; R DIV = 162
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R DIV = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
AD9520-2