AD9520-2/PCBZ Analog Devices Inc, AD9520-2/PCBZ Datasheet - Page 78
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD9520-2/PCBZ
Manufacturer Part Number
AD9520-2/PCBZ
Description
12/24 Channel Clock Gen 2,0GH
Manufacturer
Analog Devices Inc
Datasheet
1.AD9520-2BCPZ.pdf
(84 pages)
Specifications of AD9520-2/PCBZ
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9520-2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr
(Hex) Bit(s) Name
197
197
197
197
198
198
198
199
199
19A
19A
19A
19A
19A
19B
AD9520-2
[6]
[5]
[4]
[3:0]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[2]
Divider 2 ignore SYNC
Divider 2 force high
Divider 2 start high
Divider 2 phase offset
Channel 2 power-down
Channel 2 direct-to-output
Disable Divider 2 DCC
Divider 3 low cycles
Divider 3 high cycles
Divider 3 bypass
Divider 3 ignore SYNC
Divider 3 force high
Divider 3 start high
Divider 3 phase offset
Channel 3 power-down
Description
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset(default: 0x0).
Channel 2 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe power-
down mode by setting this bit.)
Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.
[1] = 0; OUT6, OUT7, and OUT8 are connected to Divider 2 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 3 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into safe
power-down mode by setting this bit.)
Rev. 0 | Page 78 of 84