AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 34

• Manufacturer Part Number: AD9520-4BCPZ-REEL7
• Description: Clock IC With 1.6GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-4BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-4
Phase-Locked Loop (PLL)
The AD9520 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9520 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited
to clean up jitter and phase noise on a noisy reference. The
exact choice of PLL parameters and loop dynamics is application
specific. The flexibility and depth of the AD9520 PLL allows
the part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9520 allows flexible configuration of the PLL,
accomodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse
width, the charge pump current, the selection of internal VCO
or external VCO/VCXO, and the loop bandwidth. These are
managed through programmable register settings (see Table 49
and Table 53) and by the design of the external loop filter.
OPTIONAL
BYPASS
REFIN
REFIN
CLK
CLK
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
BUF
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
ZERO DELAY BLOCK
2, 3, 4, 5, OR 6
P, P + 1
DIVIDE BY 1,
1
GND
0
N DIVIDER
STATUS
Figure 38. PLL Functional Block
COUNTERS
DISTRIBUTION
REFERENCE
A/B
Rev. 0 | Page 34 of 84
RSET
FROM CHANNEL
PROGRAMMABLE
DIVIDER 0
REFMON
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings, and the design of the external loop filter is crucial to
the proper operation of the PLL.
ADIsimCLK™ (V1.3 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9520, including the design of the PLL loop filter. The
AD9516 model found in ADIsimCLK Version 1.2 can also be
used for modeling the AD9520 loop filter. It is available at
www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the Phase/Frequency Detector (PFD) parameter in Table 2.
N DELAY
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
CPRSET VCP
CHARGE
PUMP
HOLD
LD
CP
STATUS
VS_DRV