AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 64

• Manufacturer Part Number: AD9520-4BCPZ-REEL7
• Description: Clock IC With 1.6GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-4BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-4
Addr
(Hex)
193
194
195
196
197
198
199
19A
19B
19C
to
1DF
VCO Divider and CLK Input
1E0
1E1
1E2
to
22A
System
230
231
Update All Registers
232
233
to
9FF
EEPROM Buffer Segment
A00
A01
A02
A03
Parameter
Divider 1 (PECL)
Divider 2 (PECL)
Divider 3 (PECL)
VCO divider
Input CLKs
Power-down
and SYNC
IO_UPDATE
EEPROM
Buffer Segment
Register 1
EEPROM
Buffer Segment
Register 2
EEPROM
Buffer Segment
Register 3
EEPROM
Buffer Segment
Register 4
Bit 7 (MSB)
Divider 1
bypass
Divider 2
bypass
Divider 3
bypass
0
0
Unused
EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)
EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)
Divider 1 Low Cycles
Divider 2 low cycles
Divider 3 low cycles
Bit 6
Divider 1
ignore
SYNC
Divider 2
ignore
SYNC
Divider 3
ignore
SYNC
Unused
Unused
Unused
Unused
Unused
Unused
Bit 5
Divider 1
force
high
Divider 2
force
high
Divider 3
force
high
Unused
(default =
1)
EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)
EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)
Rev. 0 | Page 64 of 84
Bit 4
Divider 1
start high
Divider 2
start high
Divider 3
start high
Power -
down
clock
input
section
Unused
Unused
Unused
Unused
Bit 3
Unused
Unused
Power-
down VCO
clock
interface
Disable
power-on
SYNC
Unused
Unused
Bit 2
Channel 3
power-
down
Power-
down
VCO
and CLK
Power-
down
SYNC
Channel 1
Channel 2
power-
power-
down
down
Divider 2 High Cycles
Divider 0 high cycles
Divider 3 high cycles
phase offset
phase offset
phase offset
Divider 1
Divider 2
Divider 3
Unused
Bit 1
Channel 3
direct-to-
output
Select
VCO or CLK
Power-
down
distribution
reference
Channel 1
Channel 2
direct-to-
direct-to-
VCO divider
output
output
Bit 0 (LSB)
Disable
Divider 3
DCC
Bypass VCO
divider
Soft
SYNC
IO_UPDATE
(self-clearing)
Divider 1
Divider 2
Disable
Disable
DCC
DCC
33
11
00
Default
Value
(Hex)
00
00
00
00
00
00
00
00
00
20
00
00
00
00
00
00
02
00