AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 7.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 8.
Parameter
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
LVDS = 245.76 MHz; PLL LBW = 125 Hz
LVDS = 122.88 MHz; PLL LBW = 125 Hz
LVDS = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz
CLK = 622.08 MHz
CLK = 100 MHz
CLK = 500 MHz
CLK = 200 MHz
Any LVDS Output = 622.08 MHz
Divide Ratio = 1
Any LVDS Output = 155.52 MHz
Divide Ratio = 4
Any LVDS Output = 100 MHz
Divide Ratio = 1
Any LVDS Output = 100 MHz
Divide Ratio = 5
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Min
Typ
69
116
263
242
289
Typ
87
108
146
120
151
207
157
210
295
Max
Rev. 0 | Page 10 of 76
Max
fs rms
Unit
fs rms
fs rms
fs rms
fs rms
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; measured at rising edge of clock signal
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 12 kHz to 20 MHz
Calculated from SNR of ADC method
Broadband jitter
Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include PLL and VCO
Calculated from SNR of ADC method
Broadband jitter
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz