AD9739BBC Analog Devices Inc, AD9739BBC Datasheet - Page 32
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AD9739BBC
Manufacturer Part Number
AD9739BBC
Description
14 Bit 2.5 GSPS DAC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9739BBCZ.pdf
(56 pages)
Specifications of AD9739BBC
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
980mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
160-CSPBGA
Number Of Channels
1
Resolution
14b
Interface Type
LVDS
Single Supply Voltage (typ)
3.3V
Dual Supply Voltage (typ)
Not RequiredV
Power Supply Requirement
Analog and Digital
Output Type
Current
Integral Nonlinearity Error
±1.3LSB
Single Supply Voltage (min)
3.1V
Single Supply Voltage (max)
3.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
160
Package Type
CSP-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Settling Time
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9739BBCZ
Manufacturer:
EXAR
Quantity:
101
Company:
Part Number:
AD9739BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9739BBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9739
Table 22. LVDS Receiver Control Registers (Register 0x10, Register 0x11, Register 0x12, Register 0x13, Register 0x14,
Register 0x15, Register 0x16, Register 0x17, Register 0x18)
Register
Name
LVDS_
REC_CNT1
LVDS_
REC_CNT2
LVDS_
REC_CNT3
LVDS_
REC_CNT4
LVDS_
REC_CNT5
LVDS_
REC_CNT6
LVDS_
REC_CNT7
LVDS_
REC_CNT8
LVDS_
REC_CNT9
1
Table 23. LVDS Receiver Control Register Bit Descriptions
Bit Name
SYNC_FLG_RST
SYNC_LOOP_ON
SYNC_MST/SLV
SYNC_CNT_ENA
RCVR_FLG_RST
RCVR_LOOP_ON
RCVR_CNT_ENA
RCVR_GAIN[1:0]
SYNC_GAIN[1:0]
SMP_DEL[9:0]
FINE_DEL_MID[3:0]
DCI_DEL[9:0]
FINE_DEL_SKW[3:0]
LCKTHR[3:0]
CLKDIVPH[1:0]
SYNCO_DEL[6:0]
SYNCSH_DEL[8:0]
The two-digit number is the decimal representation of the address.
Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
1
16
17
18
19
20
21
22
23
24
Read/Write
Write
Read/write
Read/write
Read/write
Write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Bit 7
SYNC_
FLG_RST
SMP_DEL[1]
SMP_DEL[9]
DCI_DEL[3]
CLKDIVPH[1]
SYNC_GAIN
[1]
N/A
SYNCSH_
DEL[0]
SYNCSH_
DEL[8]
Description
Write high then low to reset flags set by the sync controller.
0: sync controller will not loop or generate an IRQ when an error has occurred.
1: sync controller will generate an IRQ and restart and return to track mode as previous.
0: sync controller is in slave mode.
1: sync controller is in master mode.
0: sync controller is not enabled.
1: sync controller is enabled.
Write high then low to reset flags set by the receiver controller.
0: receiver controller will not loop or generate an IRQ when an error has occurred.
1: receiver controller will generate an IRQ and restart and return to track mode as previous.
0: receiver controller is not enabled.
1: receiver controller is enabled.
Sets the receiver sample tracking gain (optimal value is 1).
Sets the sync tracking gain (optimal value is 1).
Sets the sample delay value (only valid when the data receiver controller is disabled; maximum
sample delay value is 332 or 0x14C). When the data receiver controller is enabled, this represents the
starting point for the search (optimal value is 166 or 0xA6).
Sets the fine delay line mid value (optimal value is 7).
Sets the DCI delay value (only valid when the data receiver controller is disabled; maximum DCI delay
value is 332 or 0x14C). When the data receiver controller is enabled, this represents the starting point
for the search (optimal value is 166 or 0xA6).
Sets the distance between the DCI pre and post sampling.
Sets the difference between the sample and DCI delays to lock (optimal value is 2).
Sets the clock divider phase (only valid when the sync controller is disabled).
Sets the sync output delay value (only valid when the sync controller is disabled).
Sets the sync setup and hold delay value (only valid when the sync controller is disabled).
Bit 6
SYNC_
LOOP_ON
SMP_DEL [0]
SMP_DEL[8]
DCI_DEL[2]
CLKDIVPH[0]
SYNC_GAIN
[0]
SYNCO_
DEL[6]
N/A
SYNCSH_
DEL[7]
Bit 5
SYNC_
MST/SLV
FINE_DEL_
MID[3]
SMP_DEL[7]
DCI_DEL[1]
DCI_DEL[9]
SYNCOUT_
PH[1]
SYNCO_
DEL[5]
N/A
SYNCSH_
DEL[6]
Rev. 0 | Page 32 of 56
Bit 4
SYNC_
CNT_ENA
FINE_DEL_
MID[2]
SMP_DEL[6]
DCI_DEL[0]
DCI_DEL[8]
SYNCOUT_
PH[0]
SYNCO_
DEL[4]
N/A
SYNCSH_
DEL[5]
Bit 3
N/A
FINE_DEL_
MID[1]
SMP_DEL[5]
FINE_DEL_
SKW[3]
DCI_DEL[7
LCKTHR[3]
SYNCO_
DEL[3]
N/A
SYNCSH_
DEL[4]
Bit 2
RCVR_
FLG_RST
FINE_DEL_
MID[0]
SMP_DEL[4]
FINE_DEL_
SKW[2]
DCI_DEL[6]
LCKTHR[2]
SYNCO_
DEL[2]
N/A
SYNCSH_
DEL[3]
Bit 1
RCVR_
LOOP_ON
RCVR_GAIN[1]
SMP_DEL[3]
FINE_DEL_
SKW[1]
DCI_DEL[5]
LCKTHR[1]
SYNCO_
DEL[1]
N/A
SYNCSH_
DEL[2]
Bit 0
RCVR_
CNT_ENA
RCVR_GAIN[0]
SMP_DEL[2]
FINE_DEL_
SKW[0]
DCI_DEL[4]
LCKTHR[0]
SYNCO_
DEL[0]
N/A
SYNCSH_
DEL[1]