AD9739BBC Analog Devices Inc, AD9739BBC Datasheet - Page 35

• Manufacturer Part Number: AD9739BBC
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBC

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Number Of Channels: 1
• Resolution: 14b
• Interface Type: LVDS
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Integral Nonlinearity Error: ±1.3LSB
• Single Supply Voltage (min): 3.1V
• Single Supply Voltage (max): 3.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSP-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Not Compliant

Table 29. MU Controller Register Bit Descriptions
Bit Name
PHS_DET
AUTO_EN
CMP_BST
BIAS[3:0]
MU_DUTY
AUTO_EN
POS/NEG
ADJ[5:0]
Enable
Gain[1:0]
Read
Mode[1:0]
Slope
SetPhs[4:0]
SrchMode[1:0]
MUDEL[8:0]
Guard[4:0]
ContRst
Read/Write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description
0: no action.
1: enables phase detector correction (recommended to always enable).
0: no action.
1: enables the phase detector comparator boost (only valid if PHS_DET AUTO_EN is
enabled; recommended to always enable).
Manual control of the phase detector boost bias (only valid if CMP_BST is disabled).
0: no action.
1: enables the mu controller duty correction circuitry (recommended to always
enable).
0: decreases the mu controller clock duty cycle (optimal setting).
1: increases the mu controller clock duty cycle.
Manual adjust of the mu controller clock duty cycle (only valid when
MU_DUTY_AUTO_EN is disabled).
0: the mu controller is disabled.
1: the mu controller is enabled.
Sets the mu controller tracking gain (0x01 optimal setting).
0: no action.
1: read the current value of mu delay (reads the value the controller locks if enable is
set high or reads the value written into MUDEL[0:8] if enable is set low).
Sets the mode in which the mu controller functions.
0x0: search and track (optimal setting).
0x1: track only.
0x2: search only.
0x3: invalid.
0: the mu controller locks on the negative phase slope (optimal setting for best ac
performance).
1: the mu controller locks on the positive phase slope.
Sets the phase that the mu controller locks onto (maximum value is 16; optimal
setting for best ac performance is 6).
Sets the mode in which the mu controller searches for the desired phase from the
specified starting mu delay value.
0x0: down.
0x1: up.
0x2: down/up (optimal setting).
0x3: invalid.
With enable set to 0, this value represents the value that the mu delay will be set to.
With enable set to 1, this value represents the mu delay value at which the controller
will begin its search. The maximum mu delay value is 432 or 0x1B0 (it is recommended
to set this value to the midpoint to begin the search (216)).
With enable set to 0 and read set to 1, this reads back the value that was written into
the register to lock to.
With enable set to 1 and read set to 1, this value reads back the value that the mu
controller locked to.
Sets a GB from the beginning and end of the mu delay line in which the mu controller
will not enter into unless it does not find a valid phase outside the GB (optimal value is
Decimal 11 or 0x0B).
Controls whether the controller resets or continues if it does not find the desired
phase.
0x0: continue (optimal setting).
0x1: reset.
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Reset Value for
Write Register
0
0
0
0
0
0
0
0x01
0
0x0
1
0x2
0x0
0x0
0x0
AD9739