ADAV803ASTZ-REEL Analog Devices Inc, ADAV803ASTZ-REEL Datasheet - Page 17

• Manufacturer Part Number: ADAV803ASTZ-REEL
• Description: IC,Soundcard Circuits,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV803ASTZ-REEL

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV803EBZ - BOARD EVALUATION FOR ADAV803
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Selecting a Sample Rate
The output sample rate of the ADC is always ADC MCLK/256,
as shown in Figure 23. By default, the ADC modulator runs at
ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz,
the ADC modulator should be set to run at ADC MCLK/4.
This is achieved by setting the AMC (ADC Modulator Clock)
bit in the ADC Control Register 1. To compensate for the
reduced modulator clock speed, a different set of filters is used
in the decimator section, ensuring that the sample rate remains
the same.
The AMC bit can also be used to boost the THD + N perform-
ance of the ADC at the expense of dynamic range. The
improvement is typically 0.5 dB to 1.0 dB and works because
NO
INCREASE GAIN BY 0.5dB
FULLY RESTORED?
HAS GAIN BEEN
YES
YES
LIMITED RECOVERY
WAIT FOR SAMPLE
SAMPLES BELOW
HAS RECOVERY
ABOVE ATTACK
THRESHOLD?
THRESHOLD?
REACHED?
RECOVERY
IS SAMPLE
TIME BEEN
YES
ARE ALL
NO
YES
MODE ENABLED?
IS A RECOVERY
AT MAXIMUM?
IS GAINCNTR
INCREMENT
GAINCNTR
NO
NO
NO
YES
Figure 26. ALC Flow Diagram
Rev. A | Page 17 of 60
NO
ATTACK MODE
NO
DECREASE GAIN BY 0.5dB
GREATER THAN ATTACK
AND WAIT ATTACK TIME
WAIT FOR SAMPLE
THRESHOLD?
IS SAMPLE
selecting the lower modulator rate reduces the amount of digital
noise, improving THD + N, but also reduces the oversampling
ratio, therefore reducing the dynamic range by a corresponding
amount.
For best performance of the ADC, avoid using similar frequency
clocks from separate sources in the ADAV803. For example,
running the ADC from a 12.288 MHz clock connected to
MCLKI and using the PLL to generate a separate 12.288 MHz
clock for the DAC can reduce the performance of the ADC.
This is due to the interaction of the clocks, which generate beat
frequencies that can affect the charge on the switch capacitors of
the analog inputs.
NO
YES
INCREASE GAIN BY 0.5dB
WAIT RECOVERY TIME
WAIT FOR SAMPLE
FULLY RESTORED?
SAMPLES BELOW
HAS RECOVERY
HAS GAIN BEEN
ABOVE ATTACK
THRESHOLD?
THRESHOLD?
TIME BEEN
REACHED?
RECOVERY
IS SAMPLE
YES
YES
NO
ARE ALL
NORMAL RECOVERY
YES
NO
NO
ADAV803