ADAV803ASTZ-REEL Analog Devices Inc, ADAV803ASTZ-REEL Datasheet - Page 42

• Manufacturer Part Number: ADAV803ASTZ-REEL
• Description: IC,Soundcard Circuits,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV803ASTZ-REEL

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV803EBZ - BOARD EVALUATION FOR ADAV803
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAV803
Sample Rate Converter Error—Address 0011010 (0x1A)
Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map
7
Reserved
Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions
Bit Name
TOO_SLOW
OVRL
OVRR
MUTE_IND
Sample Rate Converter Error Mask—Address 0011011 (0x1B)
Table 67. Sample Rate Converter Error Mask Register Bit Map
7
Reserved
Table 68. Sample Rate Converter Error Mask Register Bit Descriptions
Bit Name
OVRL Mask
OVRR Mask
MUTE_IND MASK
6
Reserved
6
Reserved
Masks the OVRL from generating an interrupt.
Masks the OVRR from generating an interrupt.
Masks the MUTE_IND from generating an interrupt.
Description
This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
Description
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
5
Reserved
5
Reserved
4
Reserved
4
Reserved
Rev. A | Page 42 of 60
Reserved
3
3
TOO_SLOW
2
OVRL Mask
2
OVRL
1
OVRR Mask
1
OVRR
0
MUTE_IND MASK
0
MUTE_IND