ADAV803ASTZ-REEL Analog Devices Inc, ADAV803ASTZ-REEL Datasheet - Page 27

• Manufacturer Part Number: ADAV803ASTZ-REEL
• Description: IC,Soundcard Circuits,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV803ASTZ-REEL

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV803EBZ - BOARD EVALUATION FOR ADAV803
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15. Transmitter User Bit Buffer Size
TxBCONF0
0
1
By using sticky bits and interrupts, the transmit buffers can
notify the host or microcontroller about their status. The sticky
bit, TxUBINT, is set when the transmit user bit buffer has been
updated and the second transmit user bit buffer is empty and
ready to accept new user bits. This bit is located in the interrupt
status register. When the host reads the interrupt status register,
this bit is cleared. Interrupts for the TxUBINT sticky bit can be
enabled by setting the TxUBINT Mask bit in the interrupt
status mask register
Autobuffering
The ADAV803 S/PDIF receiver and transmitter sections have
an autobuffering mode allowing the channel status and user bits
to be copied automatically from the receiver to the transmitter
without user intervention. The channel status and user bits
can be independently selected for autobuffering using the
Auto_CSBits and Auto_UBits bits, respectively, in the Auto-
buffer register. When the receiver and transmitter are running
at the same sample rate, the transmitted channel status and user
bits are the same as the received channel-status and user bits.
In many systems, however, it is likely that the receiver and
transmitter are not running at the same frequency. When the
transmitter sample rate is higher than the receiver sample rate,
the channel status and user bit blocks are sometimes repeated.
When the transmitter sample rate is lower than the receiver
sample rate, the channel status and user bit blocks might be
dropped. Because the first five bytes of the channel status are
typically constant, they can be repeated or dropped with no
information loss. However, if the PRO bit in the channel status
is set and the local sample address code and time-of-day code
bytes contain information, these bytes might be repeated or
dropped, in which case information can be lost. It is up to the
user to determine how to handle this case.
ADDRESS = 0x52
ADDRESS = 0x53
TRANSMITTER USER BIT
TRANSMITTER USER BIT
INDIRECT ADDRESS
DATA REGISTER
REGISTER
Buffer Size
384 bits with Preamble Z as the start of the block.
768 bits with Preamble Z as the start of the block.
Figure 49. Transmitter User Bit Buffer
USER-BIT
BUFFER
16.....23
8.....15
0.....7
SECOND
S/PDIF 0
BUFFER
16.....23
8.....15
0.....7
Rev. A | Page 27 of 60
When the user bits are transmitted according to the IEC 60958-3
format, the messages contained in the user bits can still be sent
without dropping or repeating messages. Because zero-stuffing
is allowed between IUs and messages, zeros can be added or
subtracted to preserve the messages. When the transmitter
sample rate is greater than the receiver sample rate, extra zeros
are stuffed between the messages. When the sample rate of the
transmitter is less than the sample rate of the receiver, the zeros
stuffed between the messages are subtracted. If there are not
enough zeros between the messages to be subtracted, the zeros
between IUs are subtracted as well. The Zero_Stuff_IU bit in
the Autobuffer register enables the adding or subtracting of
zeros between messages.
Interrupts
The ADAV803 provides interrupt bits to indicate the presence
of certain conditions that require attention. Reading the
interrupt status register (Register 0x1C) allows the user to
determine if any of the interrupts have been asserted. The bits
of the Interrupt Status register remain high, if set, until the
register is read. Two bits, SRCError and RxError, indicate
interrupt conditions in the sample rate converter and an S/PDIF
receiver error, respectively. Both these conditions require a read
of the appropriate error register (Register 0x1A and Register
0x18, respectively) to determine the exact cause of the interrupt.
Each interrupt in the interrupt status register has an associated
mask bit in the interrupt status mask register. The interrupt
mask bit must be set for the corresponding interrupt to be
generated. This feature allows the user to determine which
functions should be responded to.
The dual function pin ZEROL/INT can be set to indicate the
presence of no audio data on the left channel or the presence of
an interrupt set in the interrupt status register. As shown in
Table 16, the function of this pin is selected by the INTRPT bit
in DAC Control Register 4.
Table 16. ZEROL/INT Pin Functionality
INTRPT
0
1
SERIAL DATA PORTS
The ADAV803 contains four flexible serial ports (SPORTs) to
allow data transfer to and from the codec. All four SPORTs are
independent and can be configured as master or slave ports. In
slave mode, the xLRCLK and xBCLK signals are inputs to the
serial ports. In master mode, the serial port generates the
xLRCLK and xBCLK signals. The master clock for the SPORT
can be selected from a number of sources, as shown in
Figure 50.
Pin Functionality
Pin functions as a ZEROL flag pin.
Pin functions as an interrupt pin.
ADAV803