ADCMP561BRQZ Analog Devices Inc, ADCMP561BRQZ Datasheet - Page 6

• Manufacturer Part Number: ADCMP561BRQZ
• Description: Dual High Speed PECL Comparator
• Manufacturer: Analog Devices Inc
• Type: with Latchr

Specifications of ADCMP561BRQZ

• Number Of Elements: 2
• Output Type: Complementary, Differential, Open-Emitter, PECL
• Voltage - Supply: ±4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 16-LSSOP (0.154", 3.91mm Width)
• Number Of Elements: 2
• Input Offset Voltage: 10mV
• Input Bias Current (typ): 10uA
• Response Time: 700ns
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): -5.2/5V
• Supply Current (max): 13/28@±5VmA
• Power Supply Requirement: Dual
• Common Mode Rejection Ratio: 80dB
• Voltage Gain In Db: 63dB
• Power Supply Rejection Ratio: 85dB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): -4.96/4.75V
• Dual Supply Voltage (max): -5.45/5.25V
• Power Dissipation: 250mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: QSOP
• No. Of Comparators: 2
• Ic Output Type: Differential
• Output Compatibility: PECL
• Supply Current: 3.2mA
• Supply Voltage Range: 4.75V To 5.25V
• Amplifier Case Style: QSOP
• No. Of Pins: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADCMP561BRQZ - BOARD EVALUATION ADCMP561BRQZ
• Lead Free Status / Rohs Status: Compliant

ADCMP561/ADCMP562
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
ADCMP561
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin No.
Figure 4. ADCMP561 16-Lead QSOP Pin Configuration
ADCMP562
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
–INA
+INA
LEA
LEA
V
V
QA
QA
DD
EE
1
2
3
4
5
6
7
8
ADCMP561
(Not to Scale)
TOP VIEW
Mnemonic
V
QA
QA
V
LEA
LEA
V
−INA
+INA
HYSA
HYSB
+INB
−INB
V
LEB
LEB
DD
DD
EE
CC
16
15
14
13
12
11
10
9
QB
QB
GND
LEB
LEB
V
–INB
+INB
CC
Logic Supply Terminal.
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
Logic Supply Terminal.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In the latch mode (logic low), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting
A input must be driven in conjunction with the inverting A input.
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting
B input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
Positive Supply Terminal.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to placing the comparator in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to placing the comparator in the latch mode. LEB must be
driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.
Function
Rev. A | Page 6 of 16
Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
HYSA
–INA
+INA
LEA
LEA
V
V
V
QA
QA
DD
DD
EE
10
1
2
3
4
5
6
7
8
9
ADCMP562
(Not to Scale)
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
QB
QB
GND
LEB
LEB
V
–INB
+INB
HYSB
DD
CC