ADE7569ASTZF16-RL Analog Devices Inc, ADE7569ASTZF16-RL Datasheet - Page 132

• Manufacturer Part Number: ADE7569ASTZF16-RL
• Description: IC,Power Metering,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16-RL

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569
Table 153. Port 0 Alternate Functions
Pin No.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Table 154. Port 1 Alternate Functions
Pin No.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Table 155. Port 2 Alternate Functions
Pin No.
P2.0
P2.1
P2.2
P2.3
Alternate Function
BCTRL External Battery Control Input
INT1 External Interrupt
INT1 Wake-up from PSM2 Operating Mode
FP19 LCD Segment Pin
CF1 ADE Calibration Frequency Output
CF2 ADE Calibration Frequency Output
MOSI SPI Data Line
SDATA I
MISO SPI Data Line
SCLK Serial Clock for I
T0 Timer0 Input
SS SPI Slave Select Input for SPI in Slave Mode
SS SPI Slave Select Output for SPI
in Master Mode
T1 Timer 1 Input
Alternate Function
RxD Receiver Data Input for UART
Rx Edge Wake-up from PSM2 Operating Mode
TxD Transmitter Data Output for UART
FP25 LCD Segment Pin
FP24 LCD Segment Pin
T2EX Timer 2 Control Input
FP23 LCD Segment Pin
T2 Timer 2 Input
FP22 LCD Segment Pin
FP21 LCD Segment Pin
FP20 LCD Segment Pin
Alternate Function
FP18 LCD Segment Pin
FP17 LCD Segment Pin
FP16 LCD Segment Pin
SDEN serial download pin sampled on reset. P2.3 is an output only.
2
C Data Line
2
C or SPI
Set INT1PROG[2:0] = X01 in the Interrupt Pins Configuration SFR (INTPR, 0xFF).
Clear the DISCF2 bit in the ADE energy measurement internal MODE1 Register (0x0B).
Alternate Function Enable
Set EX1 in the Interrupt Enable SFR (IE, 0xA8).
Set INT1PROG[2:0] = 11X in the Interrupt Pins Configuration SFR (INTPR, 0xFF).
Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED).
Clear the DISCF1 bit in the ADE energy measurement internal MODE1 Register (0x0B).
Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD2, 0xE9).
Clear the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the I2CEN bit in the
I
Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the SPIEN bit in the
SPI Configuration Register SFR (SPIMOD2, 0xE9).
Set the I2CEN bit in the I
SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable the I
Set the C/T0 bit in the Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
to enable T0 as an external event counter.
Set the SS_EN bit in the SPI Configuration Register SFR (SPIMOD1, 0xE8).
Set the SPIMS_b bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9).
Set the C/T1 bit in the Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
to enable T1 as an external event counter.
Rev. PrA | Page 132 of 136
Alternate Function Enable
Set the REN bit in the Serial Communications Control Register Bit Description
SFR (SCON, 0x98).
Set RXPROG[1:0]=11 in the Peripheral Configuration SFR (PERIPH, 0xF4).
This pin becomes TxD as soon as data is written into SBUF.
Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8).
Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
Set the C/T2 bit in the Timer/Counter 2 Control SFR (T2CON, 0xC8) to enable
T2 as an external event counter.
Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
2
C Mode Register SFR (I2CMOD, 0xE8).
Alternate Function Enable
Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED).
Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED).
Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,
0xED).
Enabled by default.
2
C Mode Register SFR (I2CMOD, 0xE8) or the SPIEN bit in the
Preliminary Technical Data
2
C or SPI interface.