ADF4360-7BCPZRL7 Analog Devices Inc, ADF4360-7BCPZRL7 Datasheet - Page 10

• Manufacturer Part Number: ADF4360-7BCPZRL7
• Description: IC,FREQUENCY SYNTHESIZER,BICMOS,LLCC,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-7BCPZRL7

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.8GHz
• Number Of Elements: 1
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 250MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 350 to 1800MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-7EBZ1 - BOARD EVALUATION FOR ADF4360-7
• Lead Free Status / Rohs Status: Compliant

ADF4360-7
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9 or
16/17 and is based on a synchronous 4/5 core. A value of 32/33
can be programmed but it is not useful on this part. There is a
minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with a VCO
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid. At fundamental VCO frequencies less
than 700 MHz, a value of 8/9 is best.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
where:
f
P is the preset modulus of the dual-modulus prescaler
(8/9 or 16/17).
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
f
VCO
REFIN
is the output frequency of the VCO.
is the external reference frequency oscillator.
f
VCO
=
REF
[
(
P
IN
×
NC
B
POWER-DOWN
Figure 16. Reference Input Stage
)
SW1
CONTROL
+
A
NO
]
2
×
NC
− P).
f
SW3
SW2
REFIN
100kΩ
/
R
BUFFER
TO R COUNTER
IN
pin
Rev. A | Page 10 of 28
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
( N = BP + A ) and produces an output proportional to the phase
and frequency difference between them. Figure 18 is a simpli-
fied schematic. The PFD includes a programmable delay ele-
ment that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width of
the pulse (see Table 9).
CP OUTPUT
FROM VCO
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
HI
HI
Figure 18. PFD Simplified Schematic and Timing (In Lock)
D1
D2
CLR1
CLR2
N = BP + A
N DIVIDER
MODULUS
U1
U2
CONTROL
Figure 17. A and B Counters
Q1
Q2
PROGRAMMABLE
PRESCALER
ABP1
UP
DOWN
P/P+1
DELAY
ABP2
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
5-BIT A
U3
CPGND
V
P
CHARGE
PUMP
TO PFD
CP