ADSP-21062LAB-160 Analog Devices Inc, ADSP-21062LAB-160 Datasheet - Page 42
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ADSP-21062LAB-160
Manufacturer Part Number
ADSP-21062LAB-160
Description
Digital Signal Processor(DSP) IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21062KSZ-133.pdf
(64 pages)
Specifications of ADSP-21062LAB-160
Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
225-BGA
Lead Free Status / RoHS Status
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21062LAB-160
Manufacturer:
AD
Quantity:
201
Company:
Part Number:
ADSP-21062LAB-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Serial Ports
For serial ports, see
Table
mine whether communication is possible between two devices
Table 28. Serial Ports—External Clock
1
2
3
Table 29. Serial Ports—Internal Clock
1
2
Table 30. Serial Ports—External or Internal Clock
1
Table 31. Serial Ports—External Clock
1
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Parameter
Switching Characteristics
t
t
Parameter
Switching Characteristics
t
t
t
t
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min.
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Referenced to drive edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HDTE
32,
Table
33,
Table
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup Before TCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
Table
35,
28,
Figure
Table
29,
26, and
3
Table
1
; RFS Setup Before RCLK
Figure
30,
1
1
Table
1
1, 2
1, 2
1
25. To deter-
1
1
Rev. F | Page 42 of 64 | March 2008
1
31,
1
1
1
1
1
at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay
and data setup and hold, and 3) SCLK width.
Min
3.5
4
1.5
6.5
9
2t
Min
3
Min
3
5
CLK
Min
8
1
3
3
5 V and 3.3 V
5 V and 3.3 V
5 V and 3.3 V
5 V and 3.3 V
Max
13
Max
13
16
Max
Max
Unit
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns