ADSP-21062LAB-160 Analog Devices Inc, ADSP-21062LAB-160 Datasheet - Page 44
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ADSP-21062LAB-160
Manufacturer Part Number
ADSP-21062LAB-160
Description
Digital Signal Processor(DSP) IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21062KSZ-133.pdf
(64 pages)
Specifications of ADSP-21062LAB-160
Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
225-BGA
Lead Free Status / RoHS Status
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21062LAB-160
Manufacturer:
AD
Quantity:
201
Company:
Part Number:
ADSP-21062LAB-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
RCLK
TCLK
RFS
TFS
DR
DT
TFS, RFS, DT
TCLK, RCLK
RCLK (INT)
TCLK (INT)
TCLK
TCLK
(EXT)
(INT)
t
CLKIN
t
HOFSE
HOFSI
t
DATA TRANSMIT— INTERNAL CLOCK
HDTI
DATA RECEIVE— INTERNAL CLOCK
DT
DT
DRIVE
DRIVE
EDGE
EDGE
DRIVE EDGE
SPORT DISABLE DELAY
FROM INSTRUCTION
t
t
DFSE
t
DDTI
DRIVE
EDGE
DFSI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTEN
t
t
SCLKIW
SCLKIW
t
LOW TO HIGH ONLY
DCLK
t
t
DPTR
DDTIN
t
t
t
SFSI
SFSI
SDRI
SAMPLE
SAMPLE
EDGE
EDGE
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
Rev. F | Page 44 of 64 | March 2008
t
t
t
HFSI
HFSI
HDRI
Figure 25. Serial Ports
TFS (EXT)
TCLK/RCLK
TCLK/RCLK
CLKIN
RCLK
TCLK
RFS
TFS
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
DR
DT
t
t
HOFSE
HOFSE
t
HDTE
DATA TRANSMIT— EXTERNAL CLOCK
DRIVE
DRIVE
EDGE
EDGE
DATA RECEIVE— EXTERNAL CLOCK
DRIVE EDGE
DRIVE
EDGE
t
STFSCK
t
t
t
DFSE
DFSE
DDTE
t
DDTTE
t
t
t
HTFSCK
SCLKW
SCLKW
t
DDTTI
t
t
t
SFSE
SDRE
SFSE
SAMPLE
SAMPLE
EDGE
EDGE
t
t
t
HDRE
HFSE
HFSE